rework chip id read mecanism, based on h7 branch.

allow to identify some more chips (l5, h7), but, might break..
grevaillot · Apr 12, 2020 · 5b8ade2 · 5b8ade2
1 parent 82543df
commit 5b8ade2
Show file tree

Hide file tree

Showing 3 changed files with 52 additions and 26 deletions.
diff --git a/include/stlink.h b/include/stlink.h
@@ -91,6 +91,17 @@ extern "C" {
         STLINK_FLASH_TYPE_WB
     };
 
+    enum stlink_stm32_coreid {
+        STLINK_STM32_COREID_CORTEX = 0x2ba01477,
+        STLINK_STM32_COREID_F0 = 0x0bb11477,
+        STLINK_STM32_COREID_L0 = 0x0bc11477,
+        STLINK_STM32_COREID_L5 = 0x0be12477,
+        STLINK_STM32_COREID_F1 = 0x1ba01477,
+        STLINK_STM32_COREID_F7 = 0x5ba02477,
+        STLINK_STM32_COREID_H7 = 0x6ba02477
+    };
+
+
     struct stlink_reg {
         uint32_t r[16];
         uint32_t s[32];

diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h
@@ -53,17 +53,19 @@ enum stlink_stm32_chipids {
 	STLINK_CHIPID_STM32_L0_CAT5          = 0x447,
 	STLINK_CHIPID_STM32_F0_CAN           = 0x448,
 	STLINK_CHIPID_STM32_F7               = 0x449,	/* This ID is found on the NucleoF746ZG board */
+	STLINK_CHIPID_STM32_H7442            = 0x450,   /* covers STM32H742, STM32H743/753 and STM32H750 devices */
 	STLINK_CHIPID_STM32_F7XXXX           = 0x451,
 	STLINK_CHIPID_STM32_F72XXX           = 0x452,	/* This ID is found on the NucleoF722ZE board */
 	STLINK_CHIPID_STM32_L011             = 0x457,
 	STLINK_CHIPID_STM32_F410             = 0x458,
-  STLINK_CHIPID_STM32_G0_CAT2          = 0x460, /* G070/G071/081 */
+	STLINK_CHIPID_STM32_G0_CAT2          = 0x460, /* G070/G071/081 */
 	STLINK_CHIPID_STM32_F413             = 0x463,
 	STLINK_CHIPID_STM32_G0_CAT1          = 0x466, /* G030/G031/041 */
 	STLINK_CHIPID_STM32_G4_CAT2          = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */
 	STLINK_CHIPID_STM32_G4_CAT3          = 0x469,
 	STLINK_CHIPID_STM32_L4RX             = 0x470, /* taken from the STM32L4R9I-DISCO board */
-	STLINK_CHIPID_STM32_WB55             = 0x495
+	STLINK_CHIPID_STM32_L552             = 0x472, /* covers STM32L552 and STM32L562 devices */
+	STLINK_CHIPID_STM32_WB55             = 0x495,
 };
 
 /**

diff --git a/src/common.c b/src/common.c
@@ -824,12 +824,34 @@ int stlink_core_id(stlink_t *sl) {
 int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) {
     int ret;
 
-    ret = stlink_read_debug32(sl, 0xE0042000, chip_id);
-    if (ret == -1)
-        return ret;
+	switch (sl->core_id) {
+		default:
+			ret = stlink_read_debug32(sl, 0xE0042000, chip_id);
+			break;
+		case STLINK_STM32_COREID_L0:
+		case STLINK_STM32_COREID_F0:
+			ret = stlink_read_debug32(sl, 0x40015800, chip_id);
+			break;
+		case STLINK_STM32_COREID_L5:
+			ret = stlink_read_debug32(sl, 0xE0044000, chip_id);
+			break;
+		case STLINK_STM32_COREID_H7:
+			ret = stlink_read_debug32(sl, 0x5C001000, chip_id);
+			break;
+	}
 
-    if (*chip_id == 0)
-        ret = stlink_read_debug32(sl, 0x40015800, chip_id);    //Try Corex M0 DBGMCU_IDCODE register address
+	if (ret == -1) {
+		ELOG("could not read chip id for core %#08x: %d\n", sl->core_id, ret);
+		return ret;
+	}
+
+    /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/
+    if (*chip_id == 0x411) {
+        uint32_t cpuid;
+        stlink_read_debug32(sl, 0xE000ED00, &cpuid);
+        if ((cpuid & 0xfff0) == 0xc240)
+            sl->chip_id = 0x413;
+    }
 
     return ret;
 }
@@ -858,36 +880,27 @@ int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
  * @return 0 for success, or -1 for unsupported core type.
  */
 int stlink_load_device_params(stlink_t *sl) {
-    // This seems to normally work so is unnecessary info for a normal
-    // user. Demoted to debug. -- REW
     DLOG("Loading device parameters....\n");
     const struct stlink_chipid_params *params = NULL;
     stlink_core_id(sl);
     uint32_t chip_id;
     uint32_t flash_size;
 
-    stlink_chip_id(sl, &chip_id);
+    int ret = stlink_chip_id(sl, &chip_id);
+
+    if (ret == -1) {
+        ELOG("Could not read chip id, Check target connection\n");
+    	return ret;
+	}
+
     sl->chip_id = chip_id & 0xfff;
-    /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/
-    if (sl->chip_id == 0x411) {
-        uint32_t cpuid;
-        stlink_read_debug32(sl, 0xE000ED00, &cpuid);
-        if ((cpuid  & 0xfff0) == 0xc240)
-            sl->chip_id = 0x413;
-    }
 
-    params = stlink_chipid_get_params(sl->chip_id);		// chipid.c
-    if (params == NULL) {
-        WLOG("unknown chip id! %#x\n", chip_id);
+    params = stlink_chipid_get_params(sl->chip_id);
+    if ((params == NULL) || (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN)) {
+        ELOG("Unknown or Unsupported device, Chip id:%#x\n", chip_id);
         return -1;
     }
 
-    if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) {
-        WLOG("Invalid flash type, please check device declaration\n");
-        sl->flash_size = 0;
-        return 0;
-    }
-
     // These are fixed...
     sl->flash_base = STM32_FLASH_BASE;
     sl->sram_base = STM32_SRAM_BASE;