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[HVX] Simplify constant factor before distributing #7009
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Thanks for the speedy review @steven-johnson :) |
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Thanks for the PR @rootjalex
OK to land, remaining buildbot is irrelevant |
In one of the Google generators, we are getting the following error: LLVM ERROR: Error while trying to spill V16 from class HvxVR: Cannot scavenge register without an emergency spill slot! Reverting this PR fixes the error. Any suggestions of what might be going on? @rootjalex @pranavb-ca |
Yeah, we're going to have to revert this change, at least temporarily |
This reverts commit 69b50af.
(this is speculation, I don't know the HVX backend very well other than just instruction selection) I suspect the issue can be highlighted in the test I added I can't see any other reason that this PR would cause that error, but @pranavb-ca would certainly know better than I. |
Ah, I think there is only an int8 vector-vector |
Actually, that can't be the issue, there is no vector-scalar Unfortunately, that means I have no idea how this was caused. |
Unfortunately, this failure is happening inside a heinously complicated chunk of Halide code which I can't share as-is. Getting a small repro case is gonna be challenging. |
* simplify constant factor before distributing * add simd_op_check test
) Revert "[HVX] Simplify constant factor before distributing (halide#7009)" This reverts commit 69b50af.
The handling of
widening_shift_left
in HexagonOptimize'sDistributeShiftsAsMuls
was not properly producingwidening_mul
s. This PR fixes that. Here's a small illustrative example:Compiled with target="hexagon-64-noos-no_bounds_query-no_asserts-hvx_128-hvx_v66".
Before
DistributeShiftsAsMuls
:Previously, after
DistributeShiftsAsMuls
:Previously, codegen: 3
vsxt
and 2vmpyihb.acc
Now, after
DistributeShiftsAsMuls
:Now, codegen: 2
vsxt
and 1vmpybv.acc
I also added a test to simd_op_check_hvx.