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Source tweaks for clean compilation on Verilator #12

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merged 2 commits into from
Jul 18, 2020

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jamesbowman
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Hi Sameer, I'm working on a verification testbench for your HDMI code base.
This first commit makes some small syntax changes to get to clean build with Verilator and Icarus Verilog.

The next steps are:

  • a testbench that dumps the 3 x 10 bit TMDS values for N clocks
  • a stream analyzer that verifies HDMI against the spec and the settings

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Thanks for working on this. Left some feedback. Looks good to me overall. 👍

begin
assign packet_bytes[6] = 8'hff;
assign packet_bytes[7] = 8'hff;
assign packet_bytes[8] = 8'hff;
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bytes 8, 9, 12, and 13 are supposed to be 8'd0

@sameer sameer merged commit 3214188 into hdl-util:master Jul 18, 2020
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2 participants