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fix bit mapping inconsistency in inline of AerCompiler
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hhorii committed Jun 13, 2024
1 parent 5e40517 commit 8a293ea
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Showing 3 changed files with 73 additions and 13 deletions.
61 changes: 48 additions & 13 deletions qiskit_aer/backends/aer_compiler.py
Original file line number Diff line number Diff line change
Expand Up @@ -269,9 +269,15 @@ def _inline_for_loop_op(self, instruction, parent, bit_map):
inlined_body = self._inline_circuit(body, continue_label, break_label, inner_bit_map)
if loop_parameter is not None:
inlined_body = inlined_body.assign_parameters({loop_parameter: index})
# parent.append(inlined_body, qargs, cargs)
for inst in inlined_body:
parent.append(inst, qargs, cargs)
parent.append(
inst.replace(
qubits=[inner_bit_map[bit] for bit in inst.qubits],
clbits=[inner_bit_map[bit] for bit in inst.clbits],
),
qargs,
cargs,
)
parent.append(AerMark(continue_label, len(qargs), len(cargs)), qargs, cargs)

if inlined_body is not None:
Expand All @@ -289,17 +295,18 @@ def _inline_while_loop_op(self, instruction, parent, bit_map):
continue_label = f"{loop_name}_continue"
loop_start_label = f"{loop_name}_start"
break_label = f"{loop_name}_end"
inline_bit_map = {
inner: bit_map[outer]
for inner, outer in itertools.chain(
zip(body.qubits, instruction.qubits),
zip(body.clbits, instruction.clbits),
)
}
inlined_body = self._inline_circuit(
body,
continue_label,
break_label,
{
inner: bit_map[outer]
for inner, outer in itertools.chain(
zip(body.qubits, instruction.qubits),
zip(body.clbits, instruction.clbits),
)
},
inline_bit_map,
)
qargs = [bit_map[q] for q in instruction.qubits]
cargs = [bit_map[c] for c in instruction.clbits]
Expand All @@ -323,7 +330,14 @@ def _inline_while_loop_op(self, instruction, parent, bit_map):
parent.append(AerJump(break_label, len(qargs), len(mark_cargs)), qargs, mark_cargs)
parent.append(AerMark(loop_start_label, len(qargs), len(mark_cargs)), qargs, mark_cargs)
for inst in inlined_body:
parent.append(inst, qargs, cargs)
parent.append(
inst.replace(
qubits=[inline_bit_map[bit] for bit in inst.qubits],
clbits=[inline_bit_map[bit] for bit in inst.clbits],
),
qargs,
cargs,
)
parent.append(AerJump(continue_label, len(qargs), len(mark_cargs)), qargs, mark_cargs)
parent.append(AerMark(break_label, len(qargs), len(mark_cargs)), qargs, mark_cargs)

Expand Down Expand Up @@ -373,7 +387,14 @@ def _inline_if_else_op(self, instruction, continue_label, break_label, parent, b
parent.append(AerMark(if_true_label, len(qargs), len(mark_cargs)), qargs, mark_cargs)
child = self._inline_circuit(true_body, continue_label, break_label, true_bit_map)
for inst in child.data:
parent.append(inst, qargs, cargs)
parent.append(
inst.replace(
qubits=[true_bit_map[bit] for bit in inst.qubits],
clbits=[true_bit_map[bit] for bit in inst.clbits],
),
qargs,
cargs,
)

if false_body:
false_bit_map = {
Expand All @@ -387,7 +408,14 @@ def _inline_if_else_op(self, instruction, continue_label, break_label, parent, b
parent.append(AerMark(if_else_label, len(qargs), len(mark_cargs)), qargs, mark_cargs)
child = self._inline_circuit(false_body, continue_label, break_label, false_bit_map)
for inst in child.data:
parent.append(inst, qargs, cargs)
parent.append(
inst.replace(
qubits=[false_bit_map[bit] for bit in inst.qubits],
clbits=[false_bit_map[bit] for bit in inst.clbits],
),
qargs,
cargs,
)

parent.append(AerMark(if_end_label, len(qargs), len(mark_cargs)), qargs, mark_cargs)

Expand Down Expand Up @@ -472,7 +500,14 @@ def _inline_switch_case_op(self, instruction, continue_label, break_label, paren
case_data.body, continue_label, break_label, case_data.bit_map
)
for inst in child.data:
parent.append(inst, qargs, cargs)
parent.append(
inst.replace(
qubits=[case_data.bit_map[bit] for bit in inst.qubits],
clbits=[case_data.bit_map[bit] for bit in inst.clbits],
),
qargs,
cargs,
)
parent.append(AerJump(switch_end_label, len(qargs), len(mark_cargs)), qargs, mark_cargs)

parent.append(AerMark(switch_end_label, len(qargs), len(mark_cargs)), qargs, mark_cargs)
Expand Down
Original file line number Diff line number Diff line change
@@ -0,0 +1,6 @@
---
fixes:
- |
Fix an issue of inline of ``AerCompiler``. Mappings of qubits and clbits are broken
since cf510a2 and this fix correct them by coping `CircuitInstruction` with
correct qubits and clbits. This fix resolves https://github.com/Qiskit/qiskit-aer/issues/2171.
19 changes: 19 additions & 0 deletions test/terra/backends/aer_simulator/test_control_flow.py
Original file line number Diff line number Diff line change
Expand Up @@ -1279,3 +1279,22 @@ def test_bit_not_operation(self, method):
counts = backend.run(qc).result().get_counts()
self.assertEqual(len(counts), 1)
self.assertIn("0010101", counts)


def test_bit_mapping_in_compiler(self):
"""Test different bit mappings are correctly inlined"""
parent = QuantumCircuit(5, 2)
parent.x(0)
parent.measure(0, 0)

true_body = QuantumCircuit(1, 0)
true_body.x(0)

parent.append(IfElseOp((parent.clbits[0], 1), true_body), [1], [])

parent.measure(1, 1)

simulator = self.backend()
counts = simulator.run(parent).result().get_counts()
self.assertEqual(len(counts), 1)
self.assertIn("11", counts)

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