[NFC][ubsan] Rename prefixes in test

Looks like update_cc_test_checks is being confused if it creates vars with the name matching prefix. Issue triggered with #122415
intel · Jan 10, 2025 · a4394d9 · a4394d9
1 parent 73dd730
commit a4394d9
Showing 1 changed file with 136 additions and 136 deletions.
diff --git a/clang/test/CodeGen/allow-ubsan-check.c b/clang/test/CodeGen/allow-ubsan-check.c
@@ -1,7 +1,7 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
 // RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm -o - %s -fsanitize=signed-integer-overflow,integer-divide-by-zero,null -mllvm -ubsan-guard-checks | FileCheck %s
-// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm -o - %s -fsanitize=signed-integer-overflow,integer-divide-by-zero,null -mllvm -ubsan-guard-checks -fsanitize-trap=signed-integer-overflow,integer-divide-by-zero,null | FileCheck %s --check-prefixes=TRAP
-// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm -o - %s -fsanitize=signed-integer-overflow,integer-divide-by-zero,null -mllvm -ubsan-guard-checks -fsanitize-recover=signed-integer-overflow,integer-divide-by-zero,null | FileCheck %s --check-prefixes=RECOVER
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm -o - %s -fsanitize=signed-integer-overflow,integer-divide-by-zero,null -mllvm -ubsan-guard-checks -fsanitize-trap=signed-integer-overflow,integer-divide-by-zero,null | FileCheck %s --check-prefixes=TR
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm -o - %s -fsanitize=signed-integer-overflow,integer-divide-by-zero,null -mllvm -ubsan-guard-checks -fsanitize-recover=signed-integer-overflow,integer-divide-by-zero,null | FileCheck %s --check-prefixes=REC
 
 
 // CHECK-LABEL: define dso_local i32 @div(
@@ -31,57 +31,57 @@
 // CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP0]], [[TMP1]]
 // CHECK-NEXT:    ret i32 [[DIV]]
 //
-// TRAP-LABEL: define dso_local i32 @div(
-// TRAP-SAME: i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
-// TRAP-NEXT:  entry:
-// TRAP-NEXT:    [[X_ADDR:%.*]] = alloca i32, align 4
-// TRAP-NEXT:    [[Y_ADDR:%.*]] = alloca i32, align 4
-// TRAP-NEXT:    store i32 [[X]], ptr [[X_ADDR]], align 4
-// TRAP-NEXT:    store i32 [[Y]], ptr [[Y_ADDR]], align 4
-// TRAP-NEXT:    [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
-// TRAP-NEXT:    [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
-// TRAP-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0, !nosanitize [[META2:![0-9]+]]
-// TRAP-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP0]], -2147483648, !nosanitize [[META2]]
-// TRAP-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP1]], -1, !nosanitize [[META2]]
-// TRAP-NEXT:    [[OR:%.*]] = or i1 [[TMP3]], [[TMP4]], !nosanitize [[META2]]
-// TRAP-NEXT:    [[TMP5:%.*]] = and i1 [[TMP2]], [[OR]], !nosanitize [[META2]]
-// TRAP-NEXT:    [[TMP6:%.*]] = call i1 @llvm.allow.ubsan.check(i8 3), !nosanitize [[META2]]
-// TRAP-NEXT:    [[TMP7:%.*]] = xor i1 [[TMP6]], true, !nosanitize [[META2]]
-// TRAP-NEXT:    [[TMP8:%.*]] = or i1 [[TMP5]], [[TMP7]], !nosanitize [[META2]]
-// TRAP-NEXT:    br i1 [[TMP8]], label [[CONT:%.*]], label [[TRAP:%.*]], !nosanitize [[META2]]
-// TRAP:       trap:
-// TRAP-NEXT:    call void @llvm.ubsantrap(i8 3) #[[ATTR4:[0-9]+]], !nosanitize [[META2]]
-// TRAP-NEXT:    unreachable, !nosanitize [[META2]]
-// TRAP:       cont:
-// TRAP-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP0]], [[TMP1]]
-// TRAP-NEXT:    ret i32 [[DIV]]
+// TR-LABEL: define dso_local i32 @div(
+// TR-SAME: i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
+// TR-NEXT:  entry:
+// TR-NEXT:    [[X_ADDR:%.*]] = alloca i32, align 4
+// TR-NEXT:    [[Y_ADDR:%.*]] = alloca i32, align 4
+// TR-NEXT:    store i32 [[X]], ptr [[X_ADDR]], align 4
+// TR-NEXT:    store i32 [[Y]], ptr [[Y_ADDR]], align 4
+// TR-NEXT:    [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
+// TR-NEXT:    [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
+// TR-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0, !nosanitize [[META2:![0-9]+]]
+// TR-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP0]], -2147483648, !nosanitize [[META2]]
+// TR-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP1]], -1, !nosanitize [[META2]]
+// TR-NEXT:    [[OR:%.*]] = or i1 [[TMP3]], [[TMP4]], !nosanitize [[META2]]
+// TR-NEXT:    [[TMP5:%.*]] = and i1 [[TMP2]], [[OR]], !nosanitize [[META2]]
+// TR-NEXT:    [[TMP6:%.*]] = call i1 @llvm.allow.ubsan.check(i8 3), !nosanitize [[META2]]
+// TR-NEXT:    [[TMP7:%.*]] = xor i1 [[TMP6]], true, !nosanitize [[META2]]
+// TR-NEXT:    [[TMP8:%.*]] = or i1 [[TMP5]], [[TMP7]], !nosanitize [[META2]]
+// TR-NEXT:    br i1 [[TMP8]], label [[CONT:%.*]], label [[TRAP:%.*]], !nosanitize [[META2]]
+// TR:       trap:
+// TR-NEXT:    call void @llvm.ubsantrap(i8 3) #[[ATTR4:[0-9]+]], !nosanitize [[META2]]
+// TR-NEXT:    unreachable, !nosanitize [[META2]]
+// TR:       cont:
+// TR-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP0]], [[TMP1]]
+// TR-NEXT:    ret i32 [[DIV]]
 //
-// RECOVER-LABEL: define dso_local i32 @div(
-// RECOVER-SAME: i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
-// RECOVER-NEXT:  entry:
-// RECOVER-NEXT:    [[X_ADDR:%.*]] = alloca i32, align 4
-// RECOVER-NEXT:    [[Y_ADDR:%.*]] = alloca i32, align 4
-// RECOVER-NEXT:    store i32 [[X]], ptr [[X_ADDR]], align 4
-// RECOVER-NEXT:    store i32 [[Y]], ptr [[Y_ADDR]], align 4
-// RECOVER-NEXT:    [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
-// RECOVER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
-// RECOVER-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0, !nosanitize [[META2:![0-9]+]]
-// RECOVER-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP0]], -2147483648, !nosanitize [[META2]]
-// RECOVER-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP1]], -1, !nosanitize [[META2]]
-// RECOVER-NEXT:    [[OR:%.*]] = or i1 [[TMP3]], [[TMP4]], !nosanitize [[META2]]
-// RECOVER-NEXT:    [[TMP5:%.*]] = and i1 [[TMP2]], [[OR]], !nosanitize [[META2]]
-// RECOVER-NEXT:    [[TMP6:%.*]] = call i1 @llvm.allow.ubsan.check(i8 3), !nosanitize [[META2]]
-// RECOVER-NEXT:    [[TMP7:%.*]] = xor i1 [[TMP6]], true, !nosanitize [[META2]]
-// RECOVER-NEXT:    [[TMP8:%.*]] = or i1 [[TMP5]], [[TMP7]], !nosanitize [[META2]]
-// RECOVER-NEXT:    br i1 [[TMP8]], label [[CONT:%.*]], label [[HANDLER_DIVREM_OVERFLOW:%.*]], !prof [[PROF3:![0-9]+]], !nosanitize [[META2]]
-// RECOVER:       handler.divrem_overflow:
-// RECOVER-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP0]] to i64, !nosanitize [[META2]]
-// RECOVER-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP1]] to i64, !nosanitize [[META2]]
-// RECOVER-NEXT:    call void @__ubsan_handle_divrem_overflow(ptr @[[GLOB1:[0-9]+]], i64 [[TMP9]], i64 [[TMP10]]) #[[ATTR4:[0-9]+]], !nosanitize [[META2]]
-// RECOVER-NEXT:    br label [[CONT]], !nosanitize [[META2]]
-// RECOVER:       cont:
-// RECOVER-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP0]], [[TMP1]]
-// RECOVER-NEXT:    ret i32 [[DIV]]
+// REC-LABEL: define dso_local i32 @div(
+// REC-SAME: i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
+// REC-NEXT:  entry:
+// REC-NEXT:    [[X_ADDR:%.*]] = alloca i32, align 4
+// REC-NEXT:    [[Y_ADDR:%.*]] = alloca i32, align 4
+// REC-NEXT:    store i32 [[X]], ptr [[X_ADDR]], align 4
+// REC-NEXT:    store i32 [[Y]], ptr [[Y_ADDR]], align 4
+// REC-NEXT:    [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
+// REC-NEXT:    [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
+// REC-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0, !nosanitize [[META2:![0-9]+]]
+// REC-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP0]], -2147483648, !nosanitize [[META2]]
+// REC-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP1]], -1, !nosanitize [[META2]]
+// REC-NEXT:    [[OR:%.*]] = or i1 [[TMP3]], [[TMP4]], !nosanitize [[META2]]
+// REC-NEXT:    [[TMP5:%.*]] = and i1 [[TMP2]], [[OR]], !nosanitize [[META2]]
+// REC-NEXT:    [[TMP6:%.*]] = call i1 @llvm.allow.ubsan.check(i8 3), !nosanitize [[META2]]
+// REC-NEXT:    [[TMP7:%.*]] = xor i1 [[TMP6]], true, !nosanitize [[META2]]
+// REC-NEXT:    [[TMP8:%.*]] = or i1 [[TMP5]], [[TMP7]], !nosanitize [[META2]]
+// REC-NEXT:    br i1 [[TMP8]], label [[CONT:%.*]], label [[HANDLER_DIVREM_OVERFLOW:%.*]], !prof [[PROF3:![0-9]+]], !nosanitize [[META2]]
+// REC:       handler.divrem_overflow:
+// REC-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP0]] to i64, !nosanitize [[META2]]
+// REC-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP1]] to i64, !nosanitize [[META2]]
+// REC-NEXT:    call void @__ubsan_handle_divrem_overflow(ptr @[[GLOB1:[0-9]+]], i64 [[TMP9]], i64 [[TMP10]]) #[[ATTR4:[0-9]+]], !nosanitize [[META2]]
+// REC-NEXT:    br label [[CONT]], !nosanitize [[META2]]
+// REC:       cont:
+// REC-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP0]], [[TMP1]]
+// REC-NEXT:    ret i32 [[DIV]]
 //
 int div(int x, int y) {
   return x / y;
@@ -106,42 +106,42 @@ int div(int x, int y) {
 // CHECK-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4
 // CHECK-NEXT:    ret i32 [[TMP6]]
 //
-// TRAP-LABEL: define dso_local i32 @null(
-// TRAP-SAME: ptr noundef [[X:%.*]]) #[[ATTR0]] {
-// TRAP-NEXT:  entry:
-// TRAP-NEXT:    [[X_ADDR:%.*]] = alloca ptr, align 8
-// TRAP-NEXT:    store ptr [[X]], ptr [[X_ADDR]], align 8
-// TRAP-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8
-// TRAP-NEXT:    [[TMP1:%.*]] = icmp ne ptr [[TMP0]], null, !nosanitize [[META2]]
-// TRAP-NEXT:    [[TMP2:%.*]] = call i1 @llvm.allow.ubsan.check(i8 22), !nosanitize [[META2]]
-// TRAP-NEXT:    [[TMP3:%.*]] = xor i1 [[TMP2]], true, !nosanitize [[META2]]
-// TRAP-NEXT:    [[TMP4:%.*]] = or i1 [[TMP1]], [[TMP3]], !nosanitize [[META2]]
-// TRAP-NEXT:    br i1 [[TMP4]], label [[CONT:%.*]], label [[TRAP:%.*]], !nosanitize [[META2]]
-// TRAP:       trap:
-// TRAP-NEXT:    call void @llvm.ubsantrap(i8 22) #[[ATTR4]], !nosanitize [[META2]]
-// TRAP-NEXT:    unreachable, !nosanitize [[META2]]
-// TRAP:       cont:
-// TRAP-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
-// TRAP-NEXT:    ret i32 [[TMP5]]
+// TR-LABEL: define dso_local i32 @null(
+// TR-SAME: ptr noundef [[X:%.*]]) #[[ATTR0]] {
+// TR-NEXT:  entry:
+// TR-NEXT:    [[X_ADDR:%.*]] = alloca ptr, align 8
+// TR-NEXT:    store ptr [[X]], ptr [[X_ADDR]], align 8
+// TR-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8
+// TR-NEXT:    [[TMP1:%.*]] = icmp ne ptr [[TMP0]], null, !nosanitize [[META2]]
+// TR-NEXT:    [[TMP2:%.*]] = call i1 @llvm.allow.ubsan.check(i8 22), !nosanitize [[META2]]
+// TR-NEXT:    [[TMP3:%.*]] = xor i1 [[TMP2]], true, !nosanitize [[META2]]
+// TR-NEXT:    [[TMP4:%.*]] = or i1 [[TMP1]], [[TMP3]], !nosanitize [[META2]]
+// TR-NEXT:    br i1 [[TMP4]], label [[CONT:%.*]], label [[TRAP:%.*]], !nosanitize [[META2]]
+// TR:       trap:
+// TR-NEXT:    call void @llvm.ubsantrap(i8 22) #[[ATTR4]], !nosanitize [[META2]]
+// TR-NEXT:    unreachable, !nosanitize [[META2]]
+// TR:       cont:
+// TR-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
+// TR-NEXT:    ret i32 [[TMP5]]
 //
-// RECOVER-LABEL: define dso_local i32 @null(
-// RECOVER-SAME: ptr noundef [[X:%.*]]) #[[ATTR0]] {
-// RECOVER-NEXT:  entry:
-// RECOVER-NEXT:    [[X_ADDR:%.*]] = alloca ptr, align 8
-// RECOVER-NEXT:    store ptr [[X]], ptr [[X_ADDR]], align 8
-// RECOVER-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8
-// RECOVER-NEXT:    [[TMP1:%.*]] = icmp ne ptr [[TMP0]], null, !nosanitize [[META2]]
-// RECOVER-NEXT:    [[TMP2:%.*]] = call i1 @llvm.allow.ubsan.check(i8 22), !nosanitize [[META2]]
-// RECOVER-NEXT:    [[TMP3:%.*]] = xor i1 [[TMP2]], true, !nosanitize [[META2]]
-// RECOVER-NEXT:    [[TMP4:%.*]] = or i1 [[TMP1]], [[TMP3]], !nosanitize [[META2]]
-// RECOVER-NEXT:    br i1 [[TMP4]], label [[CONT:%.*]], label [[HANDLER_TYPE_MISMATCH:%.*]], !prof [[PROF3]], !nosanitize [[META2]]
-// RECOVER:       handler.type_mismatch:
-// RECOVER-NEXT:    [[TMP5:%.*]] = ptrtoint ptr [[TMP0]] to i64, !nosanitize [[META2]]
-// RECOVER-NEXT:    call void @__ubsan_handle_type_mismatch_v1(ptr @[[GLOB2:[0-9]+]], i64 [[TMP5]]) #[[ATTR4]], !nosanitize [[META2]]
-// RECOVER-NEXT:    br label [[CONT]], !nosanitize [[META2]]
-// RECOVER:       cont:
-// RECOVER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4
-// RECOVER-NEXT:    ret i32 [[TMP6]]
+// REC-LABEL: define dso_local i32 @null(
+// REC-SAME: ptr noundef [[X:%.*]]) #[[ATTR0]] {
+// REC-NEXT:  entry:
+// REC-NEXT:    [[X_ADDR:%.*]] = alloca ptr, align 8
+// REC-NEXT:    store ptr [[X]], ptr [[X_ADDR]], align 8
+// REC-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[X_ADDR]], align 8
+// REC-NEXT:    [[TMP1:%.*]] = icmp ne ptr [[TMP0]], null, !nosanitize [[META2]]
+// REC-NEXT:    [[TMP2:%.*]] = call i1 @llvm.allow.ubsan.check(i8 22), !nosanitize [[META2]]
+// REC-NEXT:    [[TMP3:%.*]] = xor i1 [[TMP2]], true, !nosanitize [[META2]]
+// REC-NEXT:    [[TMP4:%.*]] = or i1 [[TMP1]], [[TMP3]], !nosanitize [[META2]]
+// REC-NEXT:    br i1 [[TMP4]], label [[CONT:%.*]], label [[HANDLER_TYPE_MISMATCH:%.*]], !prof [[PROF3]], !nosanitize [[META2]]
+// REC:       handler.type_mismatch:
+// REC-NEXT:    [[TMP5:%.*]] = ptrtoint ptr [[TMP0]] to i64, !nosanitize [[META2]]
+// REC-NEXT:    call void @__ubsan_handle_type_mismatch_v1(ptr @[[GLOB2:[0-9]+]], i64 [[TMP5]]) #[[ATTR4]], !nosanitize [[META2]]
+// REC-NEXT:    br label [[CONT]], !nosanitize [[META2]]
+// REC:       cont:
+// REC-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4
+// REC-NEXT:    ret i32 [[TMP6]]
 //
 int null(int* x) {
   return *x;
@@ -172,53 +172,53 @@ int null(int* x) {
 // CHECK:       cont:
 // CHECK-NEXT:    ret i32 [[TMP3]]
 //
-// TRAP-LABEL: define dso_local i32 @overflow(
-// TRAP-SAME: i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR0]] {
-// TRAP-NEXT:  entry:
-// TRAP-NEXT:    [[X_ADDR:%.*]] = alloca i32, align 4
-// TRAP-NEXT:    [[Y_ADDR:%.*]] = alloca i32, align 4
-// TRAP-NEXT:    store i32 [[X]], ptr [[X_ADDR]], align 4
-// TRAP-NEXT:    store i32 [[Y]], ptr [[Y_ADDR]], align 4
-// TRAP-NEXT:    [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
-// TRAP-NEXT:    [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
-// TRAP-NEXT:    [[TMP2:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[TMP0]], i32 [[TMP1]]), !nosanitize [[META2]]
-// TRAP-NEXT:    [[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0, !nosanitize [[META2]]
-// TRAP-NEXT:    [[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1, !nosanitize [[META2]]
-// TRAP-NEXT:    [[TMP5:%.*]] = xor i1 [[TMP4]], true, !nosanitize [[META2]]
-// TRAP-NEXT:    [[TMP6:%.*]] = call i1 @llvm.allow.ubsan.check(i8 0), !nosanitize [[META2]]
-// TRAP-NEXT:    [[TMP7:%.*]] = xor i1 [[TMP6]], true, !nosanitize [[META2]]
-// TRAP-NEXT:    [[TMP8:%.*]] = or i1 [[TMP5]], [[TMP7]], !nosanitize [[META2]]
-// TRAP-NEXT:    br i1 [[TMP8]], label [[CONT:%.*]], label [[TRAP:%.*]], !nosanitize [[META2]]
-// TRAP:       trap:
-// TRAP-NEXT:    call void @llvm.ubsantrap(i8 0) #[[ATTR4]], !nosanitize [[META2]]
-// TRAP-NEXT:    unreachable, !nosanitize [[META2]]
-// TRAP:       cont:
-// TRAP-NEXT:    ret i32 [[TMP3]]
+// TR-LABEL: define dso_local i32 @overflow(
+// TR-SAME: i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR0]] {
+// TR-NEXT:  entry:
+// TR-NEXT:    [[X_ADDR:%.*]] = alloca i32, align 4
+// TR-NEXT:    [[Y_ADDR:%.*]] = alloca i32, align 4
+// TR-NEXT:    store i32 [[X]], ptr [[X_ADDR]], align 4
+// TR-NEXT:    store i32 [[Y]], ptr [[Y_ADDR]], align 4
+// TR-NEXT:    [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
+// TR-NEXT:    [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
+// TR-NEXT:    [[TMP2:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[TMP0]], i32 [[TMP1]]), !nosanitize [[META2]]
+// TR-NEXT:    [[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0, !nosanitize [[META2]]
+// TR-NEXT:    [[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1, !nosanitize [[META2]]
+// TR-NEXT:    [[TMP5:%.*]] = xor i1 [[TMP4]], true, !nosanitize [[META2]]
+// TR-NEXT:    [[TMP6:%.*]] = call i1 @llvm.allow.ubsan.check(i8 0), !nosanitize [[META2]]
+// TR-NEXT:    [[TMP7:%.*]] = xor i1 [[TMP6]], true, !nosanitize [[META2]]
+// TR-NEXT:    [[TMP8:%.*]] = or i1 [[TMP5]], [[TMP7]], !nosanitize [[META2]]
+// TR-NEXT:    br i1 [[TMP8]], label [[CONT:%.*]], label [[TRAP:%.*]], !nosanitize [[META2]]
+// TR:       trap:
+// TR-NEXT:    call void @llvm.ubsantrap(i8 0) #[[ATTR4]], !nosanitize [[META2]]
+// TR-NEXT:    unreachable, !nosanitize [[META2]]
+// TR:       cont:
+// TR-NEXT:    ret i32 [[TMP3]]
 //
-// RECOVER-LABEL: define dso_local i32 @overflow(
-// RECOVER-SAME: i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR0]] {
-// RECOVER-NEXT:  entry:
-// RECOVER-NEXT:    [[X_ADDR:%.*]] = alloca i32, align 4
-// RECOVER-NEXT:    [[Y_ADDR:%.*]] = alloca i32, align 4
-// RECOVER-NEXT:    store i32 [[X]], ptr [[X_ADDR]], align 4
-// RECOVER-NEXT:    store i32 [[Y]], ptr [[Y_ADDR]], align 4
-// RECOVER-NEXT:    [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
-// RECOVER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
-// RECOVER-NEXT:    [[TMP2:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[TMP0]], i32 [[TMP1]]), !nosanitize [[META2]]
-// RECOVER-NEXT:    [[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0, !nosanitize [[META2]]
-// RECOVER-NEXT:    [[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1, !nosanitize [[META2]]
-// RECOVER-NEXT:    [[TMP5:%.*]] = xor i1 [[TMP4]], true, !nosanitize [[META2]]
-// RECOVER-NEXT:    [[TMP6:%.*]] = call i1 @llvm.allow.ubsan.check(i8 0), !nosanitize [[META2]]
-// RECOVER-NEXT:    [[TMP7:%.*]] = xor i1 [[TMP6]], true, !nosanitize [[META2]]
-// RECOVER-NEXT:    [[TMP8:%.*]] = or i1 [[TMP5]], [[TMP7]], !nosanitize [[META2]]
-// RECOVER-NEXT:    br i1 [[TMP8]], label [[CONT:%.*]], label [[HANDLER_ADD_OVERFLOW:%.*]], !prof [[PROF3]], !nosanitize [[META2]]
-// RECOVER:       handler.add_overflow:
-// RECOVER-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP0]] to i64, !nosanitize [[META2]]
-// RECOVER-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP1]] to i64, !nosanitize [[META2]]
-// RECOVER-NEXT:    call void @__ubsan_handle_add_overflow(ptr @[[GLOB3:[0-9]+]], i64 [[TMP9]], i64 [[TMP10]]) #[[ATTR4]], !nosanitize [[META2]]
-// RECOVER-NEXT:    br label [[CONT]], !nosanitize [[META2]]
-// RECOVER:       cont:
-// RECOVER-NEXT:    ret i32 [[TMP3]]
+// REC-LABEL: define dso_local i32 @overflow(
+// REC-SAME: i32 noundef [[X:%.*]], i32 noundef [[Y:%.*]]) #[[ATTR0]] {
+// REC-NEXT:  entry:
+// REC-NEXT:    [[X_ADDR:%.*]] = alloca i32, align 4
+// REC-NEXT:    [[Y_ADDR:%.*]] = alloca i32, align 4
+// REC-NEXT:    store i32 [[X]], ptr [[X_ADDR]], align 4
+// REC-NEXT:    store i32 [[Y]], ptr [[Y_ADDR]], align 4
+// REC-NEXT:    [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
+// REC-NEXT:    [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
+// REC-NEXT:    [[TMP2:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[TMP0]], i32 [[TMP1]]), !nosanitize [[META2]]
+// REC-NEXT:    [[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0, !nosanitize [[META2]]
+// REC-NEXT:    [[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1, !nosanitize [[META2]]
+// REC-NEXT:    [[TMP5:%.*]] = xor i1 [[TMP4]], true, !nosanitize [[META2]]
+// REC-NEXT:    [[TMP6:%.*]] = call i1 @llvm.allow.ubsan.check(i8 0), !nosanitize [[META2]]
+// REC-NEXT:    [[TMP7:%.*]] = xor i1 [[TMP6]], true, !nosanitize [[META2]]
+// REC-NEXT:    [[TMP8:%.*]] = or i1 [[TMP5]], [[TMP7]], !nosanitize [[META2]]
+// REC-NEXT:    br i1 [[TMP8]], label [[CONT:%.*]], label [[HANDLER_ADD_OVERFLOW:%.*]], !prof [[PROF3]], !nosanitize [[META2]]
+// REC:       handler.add_overflow:
+// REC-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP0]] to i64, !nosanitize [[META2]]
+// REC-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP1]] to i64, !nosanitize [[META2]]
+// REC-NEXT:    call void @__ubsan_handle_add_overflow(ptr @[[GLOB3:[0-9]+]], i64 [[TMP9]], i64 [[TMP10]]) #[[ATTR4]], !nosanitize [[META2]]
+// REC-NEXT:    br label [[CONT]], !nosanitize [[META2]]
+// REC:       cont:
+// REC-NEXT:    ret i32 [[TMP3]]
 //
 int overflow(int x, int y) {
   return x + y;
@@ -227,8 +227,8 @@ int overflow(int x, int y) {
 // CHECK: [[META2]] = !{}
 // CHECK: [[PROF3]] = !{!"branch_weights", i32 1048575, i32 1}
 //.
-// TRAP: [[META2]] = !{}
+// TR: [[META2]] = !{}
 //.
-// RECOVER: [[META2]] = !{}
-// RECOVER: [[PROF3]] = !{!"branch_weights", i32 1048575, i32 1}
+// REC: [[META2]] = !{}
+// REC: [[PROF3]] = !{!"branch_weights", i32 1048575, i32 1}
 //.