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Pull In llvm-project main #2

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merged 487 commits into from
May 16, 2022
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87d88c5
[gn build] Port 3a24df992cf8
llvmgnsyncbot May 13, 2022
4de9a8a
[InstSimplify] Add tests for and/or with implied conditions (NFC)
nikic May 13, 2022
1dce51b
[mlir] Add TensorToLinalgPass
tpopp May 11, 2022
d685215
[ArgPromotion] Add tests for already seen offsets (NFC)
samolisov May 13, 2022
1de7362
Add cmake dependency for TensorToLinalg
tpopp May 13, 2022
0485211
[IRBuilder] Remove redundant createGEP() overloads (NFC)
nikic May 13, 2022
d9ad6a2
[InstCombine] Fix unused variable warning (NFC)
nikic May 13, 2022
7b323af
[MLIR] Fix areIdsUnique in AffineStructures
Groverkss May 13, 2022
9add949
[ASTMatchers][clang-tidy][NFC] Hoist `forEachTemplateArgument` matche…
whisperity May 11, 2022
1b07bd9
[X86] Add tests for vector widening with freeze(undef)
RKSimon May 13, 2022
89d4904
[mlir] Fix declaration of nano time function in benchmark infra
shabalind May 9, 2022
562ce15
[demangler] Avoid special-subst code duplication
urnathan Mar 28, 2022
99d3582
Comment parsing: Specify argument numbers for some block commands
aaronpuchert May 13, 2022
d3a4033
Comment parsing: Allow inline commands to have 0 or more than 1 argument
aaronpuchert May 13, 2022
d2396d8
Comment parsing: Treat properties as zero-argument inline commands
aaronpuchert May 13, 2022
8e6d481
[ConstraintElimination] Simplify ssub(A,B) if B s>=b && B s>=0.
fhahn May 13, 2022
ed1cb01
[IRBuilder] Add IsInBounds parameter to CreateGEP()
nikic May 13, 2022
4be105c
Silence some false positive -Wstrict-prototype warnings
AaronBallman May 13, 2022
a80e65e
[libc++] Overhaul how we select the ABI library
ldionne Mar 1, 2022
0f9a138
fix typos to cycle bots
nico May 13, 2022
5150d65
[SLP][X86] Add common CHECK prefix to sub-128-bit vector tests
RKSimon May 13, 2022
ddfee07
[InstSimplify] Fold and/or using implied conditions
nikic May 13, 2022
92c645b
[LoopVectorize] Add overflow checks when tail-folding with scalable v…
david-arm May 6, 2022
a247ba9
Suggest typo corrections for preprocessor directives
ken-matsui May 13, 2022
afc21c7
[ControlHeightReduction] Simplify addToMergedCondition() (NFC)
nikic May 13, 2022
eaa7803
[SystemZ] Patchset for expanding memcpy/memset using at most two stores.
JonPsson Mar 8, 2022
3946de0
[MSVC] Add support for pragma function
steplong May 13, 2022
e0fcdf5
Revert "In MSVC compatibility mode, friend function declarations beha…
nico May 13, 2022
0fefb56
[InstCombine] add tests for sub with rem operand; NFC
rotateright May 12, 2022
ee6754c
[ValueTracking] recognize sub X, (X % Y) as not overflowing
rotateright May 13, 2022
d364307
Remove a stale FIXME comment; NFC
AaronBallman May 13, 2022
fcbf617
[APInt] Fix documentation of *OrSelf methods
jayfoad May 13, 2022
25862f5
Try to disambiguate between overloads on Mac
aaronpuchert May 13, 2022
e1a8d05
Update my office hours
kbeyls May 13, 2022
98f82d6
[X86] LowerStore - use is64BitVector() wrapper. NFCI.
RKSimon May 13, 2022
fe3b621
[AIX] support write operation of big archive.
diggerlin May 13, 2022
0c00dbb
[LoopVectorize] Regenerate test checks (NFC)
nikic May 13, 2022
a2ac0bb
[flang] Warn for the limit on name length
PeixinQiao May 13, 2022
7e3ea55
[clang-tidy] modernize-deprecated-headers check should respect extern…
May 13, 2022
905eff4
[x86] add test to show potential miscompile with undef value; NFC
rotateright May 13, 2022
e52e1da
[SDAG] freeze operand when expanging urem
rotateright May 13, 2022
d5ffc1e
[analyzer][NFC] Tighten some of the SValBuilder return types
May 13, 2022
a1025e6
[analyzer] Introduce clang_analyzer_dumpSvalType introspection function
May 13, 2022
e8cae48
Revert "[clang-tidy] modernize-deprecated-headers check should respec…
May 13, 2022
f01c758
[InstSimplify] Add additional implied condition tests (NFC)
nikic May 13, 2022
0d67c8a
[OpenMP] Fix declare simd use on in-class member template function
mikerice1969 May 12, 2022
1d7b5cd
[ParseResult] Mark this as LLVM_NODISCARD (like LogicalResult) and fi…
lattner May 13, 2022
af5e09b
[RISCV] Add llvm.read.register support for vlenb
preames May 13, 2022
1662cfa
[CSSPGO][CSProfileConverter] Remove call target samples when includin…
htyu May 9, 2022
f21cf11
[libc++abi][NFCI] Refactor demangling_terminate_handler to reduce nes…
ldionne May 10, 2022
0513502
[RISCV] Precommit tests showing missed vlenb optimizations
preames May 13, 2022
853fa8e
[RISCV] Address post-commit feedback from af5e09b
preames May 13, 2022
6716e20
[libunwind] Remove -Wsign-conversion warning
ldionne May 13, 2022
3fc33ce
DAGCombiner.cpp - break if-else chains that always return (style)
RKSimon May 13, 2022
534f660
[CMake] Disable libedit in Fuchsia toolchain
petrhosek May 13, 2022
a291897
Revert "[RISCV] Enable subregister liveness tracking for RVV."
topperc May 13, 2022
177fd72
[ELF] Disallow input section description without a filename
MaskRay May 13, 2022
345ed58
Fix implicit double -> float truncation warnings. NFCI.
RKSimon May 13, 2022
0a22dfc
[runtimes][NFC] Remove dead code for Standalone builds
ldionne May 13, 2022
b4f8443
[Libomptarget] Allow the device runtime to be compiled for the host
jhuber6 May 9, 2022
ce0caf4
[Libomptarget] Address existing warnings in the device runtime library
jhuber6 May 10, 2022
002a63f
[OpenMP] Add `__CUDA_ARCH__` definition when offloading with OpenMP
jhuber6 May 9, 2022
5189f63
[OpenMP] Don't include the device wrappers if -nostdinc is used
jhuber6 May 9, 2022
af757f8
[OpenMP] Don't set device runtime debugging flags if using '-nogpulib'
jhuber6 May 10, 2022
9ffa945
[Libomptarget] Remove global include directory from libomptarget
jhuber6 May 13, 2022
16b7a0b
[Libomptarget] Build the device runtime as a static library
jhuber6 May 10, 2022
4638ae3
[OpenMP] Use the new OpenMP device static library when doing LTO
jhuber6 May 10, 2022
374d789
[runtimes] Fix how we trigger CI
ldionne May 13, 2022
c1532ac
[BOLT][CMAKE] Add missing clauses to bolt/runtime/CMakeLists.txt
aaupov May 12, 2022
82482e7
[ELF][test] Clean up linkerscript/{filename-spec.s,group.s}
MaskRay May 13, 2022
912f5f7
[ELF][test] Add an input section description test with "()" in the fi…
MaskRay May 13, 2022
139744a
[BOLT][NFC] Suppress unused variable warnings
aaupov May 13, 2022
253b8f0
[BOLT][NFC] Use refs for loop variables to avoid copies
aaupov May 13, 2022
41fef10
[GlobalISel] Combine G_SHL, G_ASHR, G_SHL of undef shifts to undef.
aemerson May 5, 2022
a8abb69
[lldb] Parallelize fetching symbol files in crashlog.py
JDevlieghere May 13, 2022
2f04e70
[Clang] Add DriverKit support
egorzhdan Mar 16, 2022
da766ce
[BOLT][TEST] Fix testing on macos
aaupov May 13, 2022
f0792c7
[TableGen] Add a new json textmate description for syntax highlighting
River707 May 11, 2022
bdba3d0
[BOLT][CMAKE] Fix DYLIB build
aaupov May 13, 2022
7dc23ab
[CUDA] Add a flag to manually specify the target feature to use with …
jhuber6 May 13, 2022
54e0217
[Libomptarget] Build the static library without CUDA installed
jhuber6 May 13, 2022
85f6b15
[SLP]Do not look for buildvector sequence, if the index is reused.
alexey-bataev May 13, 2022
af845d7
[Clang] Fix DriverKit tests on Linux
egorzhdan May 13, 2022
96c2a0c
[GlobalIsel] Fix fallback if stack protector isn't supported.
efriedma-quic May 13, 2022
8a1b5f2
[llvm-ml] Add support for extern proc
alanzhao1 May 13, 2022
8b8281f
[SLP]Do not vectorize non-profitable alternate nodes.
alexey-bataev Mar 16, 2022
4205f4a
[Cuda] Add the features using the last argument
jhuber6 May 13, 2022
badd088
[GlobalOpt] Enable optimization of constructors with different priori…
alexander-shaposhnikov May 13, 2022
fc9bed0
[RISCV][NFC] Test showing wrong scheduling of expansion of memmove fo…
rofirrim May 13, 2022
189ca69
[RISCV] Use the new chain when converting a fixed RVV load
rofirrim May 13, 2022
2747887
[ParseResult] Fix warning in flang build, incorporate feedback from R…
lattner May 13, 2022
bc65fc8
[LLVM][Casting.h] Remove CastInfo pointer partial specialization.
bzcheeseman May 13, 2022
c758708
[LLVM][Casting.h] Add ForwardToPointerCast trait
bzcheeseman May 13, 2022
b074275
[llvm-ar][mri] Ensure CREATE commands overwrite the output file
bd1976bris May 13, 2022
2740c18
[NFC][Metadata] Refactor allocation, initalization and deletion of MD…
Apr 29, 2022
2601355
[clang-format][NFC] Format unit tests with insert/remove braces
owenca May 13, 2022
70b69c5
[mlir] Rename Zero* traits to Zero*s
Mogball May 14, 2022
bf8049d
[mlir][ods] (NFC) remove erroneous trait
Mogball May 14, 2022
5122738
[clang-tidy] Support expressions of literals in modernize-macro-to-enum
LegalizeAdulthood Apr 23, 2022
174cf2f
[lldb/API] Turn SBCompileUnit::GetIndexForLineEntry into FindLineEntr…
medismailben May 13, 2022
1f7f11b
[gn build] (semi-manually) port 512273833136
nico May 14, 2022
2fdc5d3
[BOLT] Fix merge-fdata handling of BAT profiles
rafaelauler May 13, 2022
acbad50
[InstCombine] [NFC] separate a function foldICmpBinOpWithConstant
ZCBing May 14, 2022
6f5f847
[libcxxabi] Copy headers into build location
petrhosek May 14, 2022
2e27094
[clang] Include clang config.h in LangStandards.cpp
porglezomp May 14, 2022
ae8bbc4
[clang] Require including config.h for CLANG_DEFAULT_STD_C
porglezomp May 14, 2022
1ecc3d8
[DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling inside…
RKSimon May 14, 2022
169ae6d
[APInt] Allow extending and truncating to the same width
jayfoad Oct 6, 2021
40e6659
[DebugInfo][Test] Simplify 'llvm/test/CodeGen/ARM/*-MergedGlobalDbg.l…
chbessonova May 14, 2022
c74753f
[lib++][doc] Fixes a link in the status paper.
mordante May 14, 2022
7ff7001
[llvm] Fix comment nits in Module class, NFC.
XiaodongLoong May 14, 2022
11ec730
[LoongArch] Add privilege instructions definition
SixWeining Apr 24, 2022
cc88212
[bazel] Port ae8bbc43f470
d0k May 14, 2022
1e462fa
[flang][driver] Switch to the MLIR coding style in the driver (nfc)
banach-space Apr 29, 2022
ac7a9ef
Resolve overload ambiguity on Mac OS when printing size_t in diagnostics
aaronpuchert May 14, 2022
5ac9d66
[DenseElementsAttr] Teach isValidRawBuffer that 1-elt values are splats.
lattner May 14, 2022
92eea11
[X86] Regenerate pull-binop-through-shift.ll showing stack address math
RKSimon May 14, 2022
6c11aeb
[libc++] Improve std::to_chars for base != 10.
mordante Feb 27, 2021
15bc3f8
[X86] rotate-extract-vector.ll - use avx512bw+avx512vl target for mor…
RKSimon May 14, 2022
0e3d1ca
[MLIR][GPU] NFC: simplify kernel operand accessor implementations.
chsigg May 6, 2022
0a1a318
[ARM] Regenerate combine-movc-sub.ll test checks
RKSimon May 14, 2022
ffacaa0
Fix unused function 'operator<<' -Wunused-function warning introduced…
RKSimon May 14, 2022
8d4d498
[DAG] Use SelectionDAG::FoldConstantArithmetic directly to match cons…
RKSimon May 14, 2022
8db72d9
[DAG] visitMUL - pull out repeated SDLoc() calls. NFC.
RKSimon May 14, 2022
16219f8
[MLIR][GPU] Add canonicalizer for gpu.memcpy
arnab-polymage May 13, 2022
f863913
[AArch64] Baseline test for D125307
arichardson May 12, 2022
0955125
[AArch64] Add missing HasNEON predicates to int->float patterns
arichardson May 12, 2022
4b5ad57
[UpdateTestChecks] Change global functions to NamelessValue members. …
arichardson May 12, 2022
f421659
[update_llc_test_checks] Baseline test for --asm-show-inst
arichardson May 12, 2022
37a6849
[update_llc_test_checks] Use FileCheck captures for MCInst/MCReg output
arichardson May 12, 2022
996873c
[UpdateTestChecks] Use a counter for unpredictable FileCheck variables
arichardson May 12, 2022
c8b4460
[AArch64] Avoid emitting MOVID when NEON is disabled
arichardson May 12, 2022
9cf17ac
[X86] Add test showing failure to reuse the same PCMPGT comparison fo…
RKSimon May 14, 2022
447c920
[lldb] Remove unused imports from crashlog.py
JDevlieghere May 13, 2022
ae016e4
[lldb] Don't swallow crashlog exceptions
JDevlieghere May 13, 2022
bc90bbb
[X86] LowerAVG - fix cut+paste typo. NFC.
RKSimon May 14, 2022
b6b0fd6
[ifs] Add --strip-size flag
abrachet May 14, 2022
1f61260
Revert "[ifs] Add --strip-size flag"
abrachet May 14, 2022
95cdd63
[DAG] visitADDLike - use SelectionDAG::FoldConstantArithmetic directl…
RKSimon May 14, 2022
60e5fd0
[RS4GC] Fix -Wunused-function in -DLLVM_ENABLE_ASSERTIONS=off build a…
MaskRay May 14, 2022
a74d9e7
[ifs] Add --strip-size flag
abrachet May 14, 2022
f4eac6e
[DAG] visitOR - merge isa/cast<ShuffleVectorSDNode> into dyn_cast<Shu…
RKSimon May 14, 2022
6e8ad98
[AMDGPU] Fix typo in cttz_zero_undef(x) -> cttz(x) fold test
RKSimon May 14, 2022
9d99cf5
[clang-tidy] Restore test parameter operator<< function (NFC)
LegalizeAdulthood May 14, 2022
5d55ffe
[libc++] Simplify the string structures a bit more
philnik777 May 14, 2022
44ae09d
[libc++][ranges][NFC] Mark completed issues related to the One Ranges…
var-const May 14, 2022
5a19fba
[RISCV] Remove unneeded check for ISD::VSCALE operand being a constan…
topperc May 14, 2022
b8f52c0
[mlir][LLVMIR] Add support for translating insert/extractvalue
mshockwave Apr 21, 2022
3da65c4
[mlir][LLVMIR] Add support for translating shufflevector
mshockwave Apr 21, 2022
c644488
Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h`
0x59616e May 15, 2022
cf0b6df
[M68k][Disassembler] Adopt the new variable length decoder
0x59616e May 15, 2022
59afc40
[LowerTypeTests][clang] Implement and allow -fsanitize=cfi-icall for …
twd2 May 15, 2022
c554aee
fix typos to cycle bots
nico May 15, 2022
b4ad450
[TargetLowering] expandCTPOP don't create an used constant mask for i…
topperc May 15, 2022
496e135
[libc++][test] Verify std::views::drop and std::views::join are CPOs
JoeLoser May 14, 2022
2cdabc0
[clang-format] Handle "if consteval { ... }" for RemoveBracesLLVM
owenca May 13, 2022
bdab5c4
ARMFixCortexA57AES1742098Pass.cpp: Suppress a warning. [-Wunused-but-…
chapuni May 15, 2022
f66596c
[clang][docs] Add escape code to fix missing '*' in reduction operati…
RKSimon May 15, 2022
da7d8de
ScalarEvolution.cpp: Reformat.
chapuni May 8, 2022
019fa34
[X86] Adjust tests for vector widening to use freeze(poison)
RKSimon May 15, 2022
df5ea2b
[X86] Add shuffles showing failure to use PERMUTE(BLEND(X,Y))
RKSimon May 15, 2022
32162cf
[X86] lowerV4I64Shuffle - try harder to lower to PERMQ(BLENDD(V1,V2))…
RKSimon May 15, 2022
c0f59be
[X86] Pull out repeated isShuffleMaskInputInPlace calls. NFC.
RKSimon May 15, 2022
3955296
[VPlan] Improve printing of VPReplicateRecipe with calls.
fhahn May 15, 2022
fd1f0c5
[X86] lowerShuffleAsLanePermuteAndSHUFP always succeeds, so just retu…
RKSimon May 15, 2022
9b44b03
[X86] Add checks to illegal-insert.ll
RKSimon May 15, 2022
6bf8133
[X86] Add test coverage for PR44915 / Issue #44260
RKSimon May 15, 2022
c748d2c
[RISCV] Improve test coverage in ctlz-cttz-ctpop.ll. NFC
topperc May 15, 2022
d0312a5
[RISCV] Add M extension command lines to ctlz-cttz-ctpop.ll. NFC
topperc May 15, 2022
b3097eb
[SLP] Fix misspelling of 'analyzed'. NFC
topperc May 15, 2022
ea18987
[flang][nfc] Fix driver method names overridden by the plugins
banach-space May 15, 2022
fd86423
Revert "[libunwind][AArch64] Add support for DWARF expression for RA_…
DanielKristofKiss May 15, 2022
fdae864
[DWARFLinker][NFC] cleanup AddressManager interface.
avl-llvm May 12, 2022
896557e
[X86] Adjust fadd costs to match SoG
RKSimon May 15, 2022
8b7c3d2
[LV] Set SCEVCheckCond to nullptr whenever it was used.
fhahn May 15, 2022
b3077f5
[X86] Move combineAddOrSubToADCOrSBB earlier. NFC.
RKSimon May 15, 2022
12e41d9
[mlir][bufferize] Infer memref types when possible
matthias-springer May 15, 2022
1878f24
[RISCV] Fix incorrect use of tail agnostic vslideup.
zakk0610 May 16, 2022
3bef90d
[Diagnostic] Warn if the size argument of memset is character literal
ChuanqiXu9 May 13, 2022
a8426ad
[RISCV][NFC] Replace for-each with array argument call.
May 12, 2022
0809f63
[LLVM][Casting.h] Add trivial self-cast
bzcheeseman May 13, 2022
924acb6
[clang] Prevent folding of non-const compound expr
May 9, 2022
49b0c60
[DivRemPairs][Mips] Pre-commit test for Mips target
tclin914 May 16, 2022
0a0d648
[Mips] Implement hasDivRemOp()
tclin914 May 16, 2022
c71f637
[gn build] Port 0a0d6489ef2e
llvmgnsyncbot May 16, 2022
7ff0bf5
[RISCV][NFC] Refactor RISC-V vector intrinsic utils.
kito-cheng May 11, 2022
e20bc89
[clang-format] Fix PointerAlignment: Right not working with tab inden…
mkurdej May 13, 2022
5bc469f
[RISCV][NFC] Fix build issue
kito-cheng May 16, 2022
9902a09
Add ThreadPriority::Low, and use QoS class Utility on Mac
May 16, 2022
40f361a
[clangd] Include Cleaner: ignore headers with IWYU export pragmas
kirillbobyrev May 16, 2022
befc952
[LoopVectorize] Permit tail-folding for low trip counts using scalabl…
david-arm Mar 10, 2022
106e63c
[clangd] NFC: Rename field to be compatible with the function name
kirillbobyrev May 16, 2022
e57f578
[clang-format] fix alignment w/o binpacked args
cha5on May 16, 2022
05c3fe0
[FastISel] Fix load folding for registers with fixups
nikic May 12, 2022
3d2e05d
[flang] Install Fortran_main library
rovka May 2, 2022
7ba4846
[ControlHeightReduction] Freeze condition when converting select to b…
nikic May 10, 2022
1a65c49
[pseudo] Support parsing variant target symbols.
hokein May 5, 2022
dfb006c
[AMDGPU] Extract SIInstrInfo::removeModOperands. NFC.
jayfoad Feb 21, 2022
c1af2d3
[AMDGPU] SIShrinkInstructions: change static functions to methods
jayfoad Feb 18, 2022
436bbce
[llvm-c] Add functions for enabling and creating opaque pointers
nico-abram May 16, 2022
71cb8c8
[clangd] parse all make_unique-like functions in preamble
upsj May 16, 2022
9dffab9
[clang-format][NFC] Don't call mightFitOnOneLine() unnecessarily
owenca May 15, 2022
8903dbe
[StatepointLowering] Properly handle local and non-local relocates of…
dantrushin May 13, 2022
4c3e51e
[AArch64] Handle 64bit vectors in tryCombineFixedPointConvert
davemgreen May 16, 2022
26a61ab
[SelectionDAG] Make getNode which uses single element SDVTList pass S…
May 16, 2022
fab5c85
[X86][AVX] Add test showing poor expansion of bit-reversal permutatio…
RKSimon May 16, 2022
f96d204
[AMDGPU][GlobalISel] Pre-commit tests for D125516
abinavpp May 13, 2022
485dd0b
[GlobalISel] Handle constant splat in funnel shift combine
abinavpp May 12, 2022
aab5bd1
[ADT] Adopt the new casting infrastructure for PointerUnion
0x59616e May 16, 2022
e473e79
[lldb][NFC] Make cmd a reference in GenerateOptionUsage
DavidSpickett May 9, 2022
4a94e38
[lldb][NFC] Simplify GenerateOptionUsage
DavidSpickett May 9, 2022
1ddc6ab
AArch64: support ISel for fence instructions
TNorthover May 16, 2022
7ff5148
[DAGCombine] Support splat_vector nodes in (and (extload)) dagcombine
brads55 May 10, 2022
ec4adf1
[InstCombine] Combine instructions of type or/and where AND masks can…
bipmis May 16, 2022
acc80ea
[AST] Cleanup on getting the underlying decl of using-shdow decl.
hokein May 16, 2022
80bebbc
[clang][NFC] Cleanup some coroutine tests
urnathan May 13, 2022
aa656f6
[runtimes] Introduce object libraries
ldionne May 11, 2022
d95513a
[RISCV] remove useless code
May 16, 2022
06400a0
[runtimes] Generalize how we reorder projects
ldionne May 6, 2022
ff3f498
[CodeGen] Use ArrayRef in TargetLowering functions
May 16, 2022
6f87261
[clang-tidy][NFC] Reimplement SimplifyBooleanExpr with RecursiveASTVi…
njames93 May 16, 2022
59c3be7
Apply clang-tidy fixes for performance-move-const-arg in SerializeToH…
joker-eph May 16, 2022
08482fa
Apply clang-tidy fixes for llvm-qualified-auto in LinalgInterfaces.cp…
joker-eph May 16, 2022
b147717
[MSVC] Add support for pragma alloc_text
steplong May 16, 2022
c702594
[AMDGPU] gfx11 BUF Instructions
Sisyph Apr 19, 2022
8ab819a
[ConstantRange] Add toKnownBits() method
nikic May 16, 2022
27fa415
[AMDGPU] Shrink MAD/FMA to MADAK/MADMK/FMAAK/FMAMK on GFX10
jayfoad Feb 18, 2022
6ef17f2
[AMDGPU] Mark sendmsg hasSideEffects. NFC
Sisyph May 13, 2022
b7315ff
[LAA,LV] Add initial support for pointer-diff memory checks.
fhahn May 16, 2022
356d47c
[ValueTracking] Handle and/or on RHS of isImpliedCondition()
nikic May 13, 2022
1520728
[SLP]Check if the root of the buildvector has one use only.
alexey-bataev May 16, 2022
242910a
[InstCombine] fix test name; NFC
rotateright May 16, 2022
325896d
[PhaseOrdering] add tests for cmp + boolean/bitwise logic; NFC
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[AArch64] Update check lines in arm64-scvt.ll. NFC
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RKSimon May 16, 2022
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[LiveIntervals] Add range accessors for value numbers [nfc]
preames May 16, 2022
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[IR] create and use helper functions that test the signbit; NFCI
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[InstrProf][NFC] Save profile bias to function map
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htyu May 13, 2022
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[RISCV] Add further trace output to InsertVSETLVI
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[DAGCombiner] Fix incorrect indentation. NFC
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[SystemZ] Patchset for expanding memcpy/memset using at most two stores.
* Set MaxStoresPerMemcpy and MaxStoresPerMemset to 2.

* Optimize stores of replicated values in SystemZ::combineSTORE(). This
  handles the now expanded memory operations and as well some other
  pre-existing cases.

* Reject a big displacement in isLegalAddressingMode() for a vector type.

* Return true from shouldConsiderGEPOffsetSplit().

Reviewed By: Ulrich Weigand

Differential Revision: https://reviews.llvm.org/D122105
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JonPsson committed May 13, 2022
commit eaa78035c6a59b0607878f463ad7b7b7444f2c60
7 changes: 4 additions & 3 deletions llvm/include/llvm/CodeGen/TargetLowering.h
Original file line number Diff line number Diff line change
@@ -3486,9 +3486,10 @@ class TargetLowering : public TargetLoweringBase {
/// Return true if the number of memory ops is below the threshold (Limit).
/// It returns the types of the sequence of memory ops to perform
/// memset / memcpy by reference.
bool findOptimalMemOpLowering(std::vector<EVT> &MemOps, unsigned Limit,
const MemOp &Op, unsigned DstAS, unsigned SrcAS,
const AttributeList &FuncAttributes) const;
virtual bool
findOptimalMemOpLowering(std::vector<EVT> &MemOps, unsigned Limit,
const MemOp &Op, unsigned DstAS, unsigned SrcAS,
const AttributeList &FuncAttributes) const;

/// Check to see if the specified operand of the specified instruction is a
/// constant integer. If so, check to see if there are any bits set in the
137 changes: 128 additions & 9 deletions llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
Original file line number Diff line number Diff line change
@@ -669,15 +669,15 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);

// We want to use MVC in preference to even a single load/store pair.
MaxStoresPerMemcpy = 0;
MaxStoresPerMemcpy = Subtarget.hasVector() ? 2 : 0;
MaxStoresPerMemcpyOptSize = 0;

// The main memset sequence is a byte store followed by an MVC.
// Two STC or MV..I stores win over that, but the kind of fused stores
// generated by target-independent code don't when the byte value is
// variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
// than "STC;MVC". Handle the choice in target-specific code instead.
MaxStoresPerMemset = 0;
MaxStoresPerMemset = Subtarget.hasVector() ? 2 : 0;
MaxStoresPerMemsetOptSize = 0;

// Default to having -disable-strictnode-mutation on
@@ -793,14 +793,17 @@ bool SystemZVectorConstantInfo::isVectorConstantLegal(
return tryValue(SplatBitsZ | Middle);
}

SystemZVectorConstantInfo::SystemZVectorConstantInfo(APFloat FPImm) {
IntBits = FPImm.bitcastToAPInt().zextOrSelf(128);
isFP128 = (&FPImm.getSemantics() == &APFloat::IEEEquad());
SplatBits = FPImm.bitcastToAPInt();
unsigned Width = SplatBits.getBitWidth();
IntBits <<= (SystemZ::VectorBits - Width);
SystemZVectorConstantInfo::SystemZVectorConstantInfo(APInt IntImm) {
if (IntImm.isSingleWord()) {
IntBits = APInt(128, IntImm.getZExtValue());
IntBits <<= (SystemZ::VectorBits - IntImm.getBitWidth());
} else
IntBits = IntImm;
assert(IntBits.getBitWidth() == 128 && "Unsupported APInt.");

// Find the smallest splat.
SplatBits = IntImm;
unsigned Width = SplatBits.getBitWidth();
while (Width > 8) {
unsigned HalfSize = Width / 2;
APInt HighValue = SplatBits.lshr(HalfSize).trunc(HalfSize);
@@ -976,7 +979,8 @@ bool SystemZTargetLowering::isLegalAddressingMode(const DataLayout &DL,
if (!isInt<20>(AM.BaseOffs))
return false;

AddressingMode SupportedAM(true, true);
bool RequireD12 = Subtarget.hasVector() && Ty->isVectorTy();
AddressingMode SupportedAM(!RequireD12, true);
if (I != nullptr)
SupportedAM = supportedAddressingMode(I, Subtarget.hasVector());

@@ -991,6 +995,28 @@ bool SystemZTargetLowering::isLegalAddressingMode(const DataLayout &DL,
return AM.Scale == 0 || AM.Scale == 1;
}

bool SystemZTargetLowering::findOptimalMemOpLowering(
std::vector<EVT> &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS,
unsigned SrcAS, const AttributeList &FuncAttributes) const {
const int MVCFastLen = 16;

// Don't expand Op into scalar loads/stores in these cases:
if (Op.isMemcpy() && Op.allowOverlap() && Op.size() <= MVCFastLen)
return false; // Small memcpy: Use MVC
if (Op.isMemset() && Op.size() - 1 <= MVCFastLen)
return false; // Small memset (first byte with STC/MVI): Use MVC
if (Op.isZeroMemset())
return false; // Memset zero: Use XC

return TargetLowering::findOptimalMemOpLowering(MemOps, Limit, Op, DstAS,
SrcAS, FuncAttributes);
}

EVT SystemZTargetLowering::getOptimalMemOpType(const MemOp &Op,
const AttributeList &FuncAttributes) const {
return Subtarget.hasVector() ? MVT::v2i64 : MVT::Other;
}

bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
return false;
@@ -6329,6 +6355,23 @@ static bool isVectorElementSwap(ArrayRef<int> M, EVT VT) {
return true;
}

static bool isOnlyUsedByStores(SDValue StoredVal, SelectionDAG &DAG) {
for (auto *U : StoredVal->uses()) {
if (StoreSDNode *ST = dyn_cast<StoreSDNode>(U)) {
EVT CurrMemVT = ST->getMemoryVT().getScalarType();
if (CurrMemVT.isRound() && CurrMemVT.getStoreSize() <= 16)
continue;
} else if (isa<BuildVectorSDNode>(U)) {
SDValue BuildVector = SDValue(U, 0);
if (DAG.isSplatValue(BuildVector, true/*AllowUndefs*/) &&
isOnlyUsedByStores(BuildVector, DAG))
continue;
}
return false;
}
return true;
}

SDValue SystemZTargetLowering::combineSTORE(
SDNode *N, DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
@@ -6387,6 +6430,82 @@ SDValue SystemZTargetLowering::combineSTORE(
}
}

// Replicate a reg or immediate with VREP instead of scalar multiply or
// immediate load. It seems best to do this during the first DAGCombine as
// it is straight-forward to handle the zero-extend node in the initial
// DAG, and also not worry about the keeping the new MemVT legal (e.g. when
// extracting an i16 element from a v16i8 vector).
if (Subtarget.hasVector() && DCI.Level == BeforeLegalizeTypes &&
isOnlyUsedByStores(Op1, DAG)) {
SDValue Word = SDValue();
EVT WordVT;

// Find a replicated immediate and return it if found in Word and its
// type in WordVT.
auto FindReplicatedImm = [&](ConstantSDNode *C, unsigned TotBytes) {
// Some constants are better handled with a scalar store.
if (C->getAPIntValue().getBitWidth() > 64 || C->isAllOnes() ||
isInt<16>(C->getSExtValue()) || MemVT.getStoreSize() <= 2)
return;
SystemZVectorConstantInfo VCI(APInt(TotBytes * 8, C->getZExtValue()));
if (VCI.isVectorConstantLegal(Subtarget) &&
VCI.Opcode == SystemZISD::REPLICATE) {
Word = DAG.getConstant(VCI.OpVals[0], SDLoc(SN), MVT::i32);
WordVT = VCI.VecVT.getScalarType();
}
};

// Find a replicated register and return it if found in Word and its type
// in WordVT.
auto FindReplicatedReg = [&](SDValue MulOp) {
EVT MulVT = MulOp.getValueType();
if (MulOp->getOpcode() == ISD::MUL &&
(MulVT == MVT::i16 || MulVT == MVT::i32 || MulVT == MVT::i64)) {
// Find a zero extended value and its type.
SDValue LHS = MulOp->getOperand(0);
if (LHS->getOpcode() == ISD::ZERO_EXTEND)
WordVT = LHS->getOperand(0).getValueType();
else if (LHS->getOpcode() == ISD::AssertZext)
WordVT = cast<VTSDNode>(LHS->getOperand(1))->getVT();
else
return;
// Find a replicating constant, e.g. 0x00010001.
if (auto *C = dyn_cast<ConstantSDNode>(MulOp->getOperand(1))) {
SystemZVectorConstantInfo VCI(
APInt(MulVT.getSizeInBits(), C->getZExtValue()));
if (VCI.isVectorConstantLegal(Subtarget) &&
VCI.Opcode == SystemZISD::REPLICATE && VCI.OpVals[0] == 1 &&
WordVT == VCI.VecVT.getScalarType())
Word = DAG.getZExtOrTrunc(LHS->getOperand(0), SDLoc(SN), WordVT);
}
}
};

if (isa<BuildVectorSDNode>(Op1) &&
DAG.isSplatValue(Op1, true/*AllowUndefs*/)) {
SDValue SplatVal = Op1->getOperand(0);
if (auto *C = dyn_cast<ConstantSDNode>(SplatVal))
FindReplicatedImm(C, SplatVal.getValueType().getStoreSize());
else
FindReplicatedReg(SplatVal);
} else {
if (auto *C = dyn_cast<ConstantSDNode>(Op1))
FindReplicatedImm(C, MemVT.getStoreSize());
else
FindReplicatedReg(Op1);
}

if (Word != SDValue()) {
assert(MemVT.getSizeInBits() % WordVT.getSizeInBits() == 0 &&
"Bad type handling");
unsigned NumElts = MemVT.getSizeInBits() / WordVT.getSizeInBits();
EVT SplatVT = EVT::getVectorVT(*DAG.getContext(), WordVT, NumElts);
SDValue SplatVal = DAG.getSplatVector(SplatVT, SDLoc(SN), Word);
return DAG.getStore(SN->getChain(), SDLoc(SN), SplatVal,
SN->getBasePtr(), SN->getMemOperand());
}
}

return SDValue();
}

15 changes: 13 additions & 2 deletions llvm/lib/Target/SystemZ/SystemZISelLowering.h
Original file line number Diff line number Diff line change
@@ -457,6 +457,12 @@ class SystemZTargetLowering : public TargetLowering {
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
MachineMemOperand::Flags Flags,
bool *Fast) const override;
bool
findOptimalMemOpLowering(std::vector<EVT> &MemOps, unsigned Limit,
const MemOp &Op, unsigned DstAS, unsigned SrcAS,
const AttributeList &FuncAttributes) const override;
EVT getOptimalMemOpType(const MemOp &Op,
const AttributeList &FuncAttributes) const override;
bool isTruncateFree(Type *, Type *) const override;
bool isTruncateFree(EVT, EVT) const override;

@@ -467,6 +473,8 @@ class SystemZTargetLowering : public TargetLowering {
return VT == MVT::i32 || VT == MVT::i64;
}

bool shouldConsiderGEPOffsetSplit() const override { return true; }

const char *getTargetNodeName(unsigned Opcode) const override;
std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
@@ -767,12 +775,15 @@ struct SystemZVectorConstantInfo {
APInt SplatUndef; // Bits correspoding to undef operands of the BVN.
unsigned SplatBitSize = 0;
bool isFP128 = false;

public:
unsigned Opcode = 0;
SmallVector<unsigned, 2> OpVals;
MVT VecVT;
SystemZVectorConstantInfo(APFloat FPImm);
SystemZVectorConstantInfo(APInt IntImm);
SystemZVectorConstantInfo(APFloat FPImm)
: SystemZVectorConstantInfo(FPImm.bitcastToAPInt()) {
isFP128 = (&FPImm.getSemantics() == &APFloat::IEEEquad());
}
SystemZVectorConstantInfo(BuildVectorSDNode *BVN);
bool isVectorConstantLegal(const SystemZSubtarget &Subtarget);
};
24 changes: 24 additions & 0 deletions llvm/test/CodeGen/SystemZ/codegenprepare-gepoffs-split.ll
Original file line number Diff line number Diff line change
@@ -0,0 +1,24 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
;
; Test that the big offsets are handled by only one AGFI.

define void @fun(i64* %Src, i64* %Dst) {
; CHECK-LABEL: fun:
; CHECK: # %bb.0:
; CHECK-NEXT: agfi %r2, 1048576
; CHECK-NEXT: lg %r0, 0(%r2)
; CHECK-NEXT: stg %r0, 0(%r3)
; CHECK-NEXT: lg %r0, 8(%r2)
; CHECK-NEXT: stg %r0, 0(%r3)
; CHECK-NEXT: br %r14
%S0 = getelementptr i64, i64* %Src, i64 131072
%V0 = load i64, i64* %S0
store volatile i64 %V0, i64* %Dst

%S1 = getelementptr i64, i64* %Src, i64 131073
%V1 = load i64, i64* %S1
store volatile i64 %V1, i64* %Dst

ret void
}
29 changes: 29 additions & 0 deletions llvm/test/CodeGen/SystemZ/dag-combine-06.ll
Original file line number Diff line number Diff line change
@@ -0,0 +1,29 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
;
; Test that DAGCombiner does not change the addressing as the displacements
; are known to be out of range. Only one addition is needed.

define void @fun(<2 x i64>* %Src, <2 x i64>* %Dst) {
; CHECK-LABEL: fun:
; CHECK: # %bb.0:
; CHECK-NEXT: aghi %r2, 4096
; CHECK-NEXT: vl %v0, 0(%r2), 3
; CHECK-NEXT: vst %v0, 0(%r3), 3
; CHECK-NEXT: vl %v0, 16(%r2), 3
; CHECK-NEXT: vst %v0, 0(%r3), 3
; CHECK-NEXT: br %r14
%1 = bitcast <2 x i64>* %Src to i8*

%splitgep = getelementptr i8, i8* %1, i64 4096
%2 = bitcast i8* %splitgep to <2 x i64>*
%V0 = load <2 x i64>, <2 x i64>* %2, align 8
store volatile <2 x i64> %V0, <2 x i64>* %Dst, align 8

%3 = getelementptr i8, i8* %splitgep, i64 16
%4 = bitcast i8* %3 to <2 x i64>*
%V1 = load <2 x i64>, <2 x i64>* %4, align 8
store volatile <2 x i64> %V1, <2 x i64>* %Dst, align 8

ret void
}
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