litex-hub · Dolu1990 · Nov 20, 2023 · Nov 14, 2023 · Nov 14, 2023 · Nov 14, 2023
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv.v b/pythondata_cpu_vexriscv/verilog/VexRiscv.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebugHwBP.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebugHwBP.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebugHwBP.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebugHwBP.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Secure.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Secure.v
diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SecureDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SecureDebug.v
diff --git a/pythondata_cpu_vexriscv/verilog/build.sbt b/pythondata_cpu_vexriscv/verilog/build.sbt
@@ -1,11 +1,11 @@
-val spinalVersion = "1.6.0"
+val spinalVersion = "1.9.4"
 
 lazy val root = (project in file(".")).
   settings(
     inThisBuild(List(
       organization := "com.github.spinalhdl",
       scalaVersion := "2.11.12",
-      version      := "0.1.0-SNAPSHOT"
+      version      := "2.0.0"
     )),
     name := "VexRiscvOnWishbone",
     libraryDependencies ++= Seq(

diff --git a/pythondata_cpu_vexriscv/verilog/ext/VexRiscv b/pythondata_cpu_vexriscv/verilog/ext/VexRiscv
diff --git a/pythondata_cpu_vexriscv/verilog/project/build.properties b/pythondata_cpu_vexriscv/verilog/project/build.properties
@@ -1 +1 @@
-sbt.version=1.2.7
+sbt.version=1.9.7
diff --git a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala
@@ -27,6 +27,7 @@ case class ArgConfig(
   dCacheSize : Int = 4096,
   pmpRegions : Int = 0,
   pmpGranularity : Int = 256,
+  pmpAddressMatchingModes : String = "na4,napot,tor",
   mulDiv : Boolean = true,
   cfu : Boolean = false,
   atomics: Boolean = false,
@@ -68,6 +69,7 @@ object GenCoreDefault{
       opt[Int]("dCacheSize")     action { (v, c) => c.copy(dCacheSize = v) } text("Set data cache size, 0 mean no cache")
       opt[Int]("pmpRegions")    action { (v, c) => c.copy(pmpRegions = v)   } text("Number of PMP regions, 0 disables PMP")
       opt[Int]("pmpGranularity")    action { (v, c) => c.copy(pmpGranularity = v)   } text("Granularity of PMP regions (in bytes)")
+      opt[String]("pmpAddressMatchingModes")    action { (v, c) => c.copy(pmpAddressMatchingModes = v)   } text("Which PMP address matching modes to support (comma-separated, out of [NA4, NAPOT, TOR])")
       opt[Boolean]("mulDiv")    action { (v, c) => c.copy(mulDiv = v)   } text("set RV32IM")
       opt[Boolean]("cfu")       action { (v, c) => c.copy(cfu = v)   } text("If true, add custom function unit interface")
       opt[Boolean]("atomics")    action { (v, c) => c.copy(atomics = v)   } text("set RV32I[A]")
@@ -159,9 +161,30 @@ object GenCoreDefault{
         },
         if (linux) new MmuPlugin(
           ioRange = (x => x(31 downto 28) === 0xB || x(31 downto 28) === 0xE || x(31 downto 28) === 0xF)
-        ) else if (argConfig.pmpRegions > 0) new PmpPlugin(
-          regions = argConfig.pmpRegions, granularity = argConfig.pmpGranularity, ioRange = _.msb
-        ) else new StaticMemoryTranslatorPlugin(
+        ) else if (argConfig.pmpRegions > 0) {
+          val splitModes = argConfig.pmpAddressMatchingModes.toLowerCase().split(",");
+
+          // Ensure the user didn't request any unsupported modes
+          val unknownModes = splitModes.filterNot(s => List("na4", "napot", "tor").contains(s));
+          if (unknownModes.length > 0) {
+            throw new Exception("Unknown PMP addressing mode: " + unknownModes(0));
+          }
+
+          if (splitModes.sameElements(List("napot"))) {
+            println("Using optimized PmpPluginNapot, supporting only the NAPOT addressing mode.");
+            new PmpPluginNapot(
+              regions = argConfig.pmpRegions,
+              granularity = argConfig.pmpGranularity,
+              ioRange = _.msb
+            )
+          } else {
+            println("Using PmpPlugin supporting the NA4, NAPOT, and TOR addressing modes.");
+            println("This will ignore the pmpGranularity argument and have 4-byte granularity.");
+            new PmpPlugin (
+              regions = 16, ioRange = _.msb
+            )
+          }
+        } else new StaticMemoryTranslatorPlugin(
           ioRange      = _.msb
         ),
+159 −2		README.md
+1 −1		build.sbt
+1 −0		doc/diagram.drawio
+2 −2		doc/nativeJtag/README.md
+106 −0		doc/vjtag/README.md
+1 −1		project/build.properties
+0 −1		project/plugins.sbt
+12 −4		src/main/scala/vexriscv/Riscv.scala
+14 −0		src/main/scala/vexriscv/Services.scala
+1 −1		src/main/scala/vexriscv/Stage.scala
+19 −2		src/main/scala/vexriscv/TestsWorkspace.scala
+3 −0		src/main/scala/vexriscv/VexRiscv.scala
+43 −11		src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
+6 −6		src/main/scala/vexriscv/demo/GenCustomInterrupt.scala
+128 −0		src/main/scala/vexriscv/demo/GenFullWithOfficialRiscvDebug.scala
+100 −0		src/main/scala/vexriscv/demo/GenFullWithTcm.scala
+97 −0		src/main/scala/vexriscv/demo/GenFullWithTcmIntegrated.scala
+0 −1		src/main/scala/vexriscv/demo/GenSecure.scala
+12 −0		src/main/scala/vexriscv/demo/Linux.scala
+69 −75		src/main/scala/vexriscv/demo/SynthesisBench.scala
+1 −1		src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala
+164 −0		src/main/scala/vexriscv/demo/VexRiscvAxi4LinuxPlicClint.scala
+14 −0		src/main/scala/vexriscv/demo/WhiteboxPlugin.scala
+94 −18		src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
+27 −9		src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
+21 −14		src/main/scala/vexriscv/ip/DataCache.scala
+23 −10		src/main/scala/vexriscv/ip/fpu/FpuCore.scala
+1 −0		src/main/scala/vexriscv/ip/fpu/Interface.scala
+6 −3		src/main/scala/vexriscv/plugin/BranchPlugin.scala
+5 −3		src/main/scala/vexriscv/plugin/CfuPlugin.scala
+477 −58		src/main/scala/vexriscv/plugin/CsrPlugin.scala
+153 −10		src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
+21 −13		src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
+16 −3		src/main/scala/vexriscv/plugin/DebugPlugin.scala
+103 −0		src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala
+24 −7		src/main/scala/vexriscv/plugin/Fetcher.scala
+1 −1		src/main/scala/vexriscv/plugin/FormalPlugin.scala
+132 −19		src/main/scala/vexriscv/plugin/FpuPlugin.scala
+7 −1		src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
+5 −2		src/main/scala/vexriscv/plugin/Misc.scala
+14 −7		src/main/scala/vexriscv/plugin/MmuPlugin.scala
+164 −202		src/main/scala/vexriscv/plugin/PmpPlugin.scala
+307 −0		src/main/scala/vexriscv/plugin/PmpPluginNapot.scala
+0 −244		src/main/scala/vexriscv/plugin/PmpPluginOld.scala
+2 −2		src/test/cpp/common/jtag.h
+2 −2		src/test/cpp/custom/atomic/src/crt.S
+1,403 −370		src/test/cpp/raw/mmu/build/mmu.asm
+499 −235		src/test/cpp/raw/mmu/build/mmu.hex
+71 −85		src/test/cpp/raw/mmu/src/crt.S
+4 −0		src/test/cpp/raw/privSpec/.gitignore
+142 −0		src/test/cpp/raw/privSpec/build/privSpec.hex
+5 −0		src/test/cpp/raw/privSpec/makefile
+328 −0		src/test/cpp/raw/privSpec/src/crt.S
+16 −0		src/test/cpp/raw/privSpec/src/ld
+159 −0		src/test/cpp/raw/privSpec/src/privileged.h
+94 −0		src/test/cpp/raw/privSpec/src/riscv_asm.h
+188 −0		src/test/cpp/regression/jtag.h
+87 −24		src/test/cpp/regression/main.cpp
+11 −0		src/test/cpp/regression/makefile
+13,463 −0		src/test/resources/asm/mmu.asm
+3,495 −4,789		src/test/resources/hex/mmu.hex
+21 −4		src/test/scala/vexriscv/TestIndividualFeatures.scala
+1 −0		src/test/scala/vexriscv/experimental/PlicCost.scala
+62 −50		src/test/scala/vexriscv/ip/fpu/FpuTest.scala