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[Arc] StateOp: latency instead of lat in assembly format (#6562)
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Spelling out latency should make it easier to understand what this
attribute means.
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@maerhart
maerhart authored Jan 12, 2024
1 parent cc93794 commit c07347a
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Showing 14 changed files with 214 additions and 214 deletions.
4 changes: 2 additions & 2 deletions include/circt/Dialect/Arc/ArcOps.td
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Expand Up @@ -147,7 +147,7 @@ def StateOp : ArcOp<"state", [

let assemblyFormat = [{
$arc `(` $inputs `)` (`clock` $clock^)? (`enable` $enable^)?
(`reset` $reset^)? `lat` $latency attr-dict
(`reset` $reset^)? `latency` $latency attr-dict
`:` functional-type($inputs, results)
}];

Expand Down Expand Up @@ -326,7 +326,7 @@ def MemoryWritePortOp : ArcOp<"memory_write_port", [

let assemblyFormat = [{
$memory `,` $arc `(` $inputs `)` (`clock` $clock^)? (`enable` $enable^)?
(`mask` $mask^)? `lat` $latency attr-dict `:`
(`mask` $mask^)? `latency` $latency attr-dict `:`
type($memory) `,` type($inputs)
}];

Expand Down
2 changes: 1 addition & 1 deletion test/Conversion/ConvertToArcs/convert-to-arcs-names.mlir
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Expand Up @@ -3,7 +3,7 @@

// CHECK-LABEL: hw.module @Trivial(
hw.module @Trivial(in %clock: !seq.clock, in %i0: i4, in %reset: i1, out o0: i4) {
// CHECK: arc.state {{@.+}}(%i0) clock %clock lat 1
// CHECK: arc.state {{@.+}}(%i0) clock %clock latency 1
// CHECK-TAP-OFF-NOT: names = ["foo"]
// CHECK-TAP-ON: names = ["foo"]
%foo = seq.compreg %i0, %clock : i4
Expand Down
20 changes: 10 additions & 10 deletions test/Conversion/ConvertToArcs/convert-to-arcs.mlir
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Expand Up @@ -71,8 +71,8 @@ hw.module @SplitAtConstants(out z: i4) {

// CHECK-LABEL: hw.module @Pipeline
hw.module @Pipeline(in %clock: !seq.clock, in %i0: i4, in %i1: i4, out z: i4) {
// CHECK-NEXT: [[S0:%.+]] = arc.state @Pipeline_arc(%i0, %i1) clock %clock lat 1
// CHECK-NEXT: [[S1:%.+]] = arc.state @Pipeline_arc_0([[S0]], %i0) clock %clock lat 1
// CHECK-NEXT: [[S0:%.+]] = arc.state @Pipeline_arc(%i0, %i1) clock %clock latency 1
// CHECK-NEXT: [[S1:%.+]] = arc.state @Pipeline_arc_0([[S0]], %i0) clock %clock latency 1
// CHECK-NEXT: [[S2:%.+]] = arc.call @Pipeline_arc_1([[S1]], %i1)
// CHECK-NEXT: hw.output [[S2]]
%0 = comb.add %i0, %i1 : i4
Expand All @@ -96,8 +96,8 @@ hw.module @Pipeline(in %clock: !seq.clock, in %i0: i4, in %i1: i4, out z: i4) {
// CHECK-LABEL: hw.module @Reshuffling
hw.module @Reshuffling(in %clockA: !seq.clock, in %clockB: !seq.clock, out z0: i4, out z1: i4, out z2: i4, out z3: i4) {
// CHECK-NEXT: hw.instance "x" @Reshuffling2()
// CHECK-NEXT: arc.state @Reshuffling_arc(%x.z0, %x.z1) clock %clockA lat 1
// CHECK-NEXT: arc.state @Reshuffling_arc_0(%x.z2, %x.z3) clock %clockB lat 1
// CHECK-NEXT: arc.state @Reshuffling_arc(%x.z0, %x.z1) clock %clockA latency 1
// CHECK-NEXT: arc.state @Reshuffling_arc_0(%x.z2, %x.z3) clock %clockB latency 1
// CHECK-NEXT: hw.output
%x.z0, %x.z1, %x.z2, %x.z3 = hw.instance "x" @Reshuffling2() -> (z0: i4, z1: i4, z2: i4, z3: i4)
%4 = seq.compreg %x.z0, %clockA : i4
Expand Down Expand Up @@ -130,8 +130,8 @@ hw.module.extern private @Reshuffling2(out z0: i4, out z1: i4, out z2: i4, out z
hw.module @FactorOutCommonOps(in %clock: !seq.clock, in %i0: i4, in %i1: i4, out o0: i4, out o1: i4) {
// CHECK-DAG: [[T0:%.+]] = arc.call @FactorOutCommonOps_arc_1(%i0, %i1)
%0 = comb.add %i0, %i1 : i4
// CHECK-DAG: [[T1:%.+]] = arc.state @FactorOutCommonOps_arc([[T0]], %i0) clock %clock lat 1
// CHECK-DAG: [[T2:%.+]] = arc.state @FactorOutCommonOps_arc_0([[T0]], %i1) clock %clock lat 1
// CHECK-DAG: [[T1:%.+]] = arc.state @FactorOutCommonOps_arc([[T0]], %i0) clock %clock latency 1
// CHECK-DAG: [[T2:%.+]] = arc.state @FactorOutCommonOps_arc_0([[T0]], %i1) clock %clock latency 1
%1 = comb.xor %0, %i0 : i4
%2 = comb.mul %0, %i1 : i4
%3 = seq.compreg %1, %clock : i4
Expand Down Expand Up @@ -171,7 +171,7 @@ hw.module.extern private @SplitAtInstance2(in %a: i4, out z: i4)
// CHECK-LABEL: hw.module @AbsorbNames
hw.module @AbsorbNames(in %clock: !seq.clock) {
// CHECK-NEXT: %x.z0, %x.z1 = hw.instance "x" @AbsorbNames2()
// CHECK-NEXT: arc.state @AbsorbNames_arc(%x.z0, %x.z1) clock %clock lat 1
// CHECK-NEXT: arc.state @AbsorbNames_arc(%x.z0, %x.z1) clock %clock latency 1
// CHECK-SAME: {names = ["myRegA", "myRegB"]}
// CHECK-NEXT: hw.output
%x.z0, %x.z1 = hw.instance "x" @AbsorbNames2() -> (z0: i4, z1: i4)
Expand All @@ -188,7 +188,7 @@ hw.module.extern @AbsorbNames2(out z0: i4, out z1: i4)

// CHECK-LABEL: hw.module @Trivial(
hw.module @Trivial(in %clock: !seq.clock, in %i0: i4, in %reset: i1, out out: i4) {
// CHECK: [[RES0:%.+]] = arc.state @[[TRIVIAL_ARC]](%i0) clock %clock reset %reset lat 1 {names = ["foo"]
// CHECK: [[RES0:%.+]] = arc.state @[[TRIVIAL_ARC]](%i0) clock %clock reset %reset latency 1 {names = ["foo"]
// CHECK-NEXT: hw.output [[RES0:%.+]]
%0 = hw.constant 0 : i4
%foo = seq.compreg %i0, %clock reset %reset, %0 : i4
Expand All @@ -206,8 +206,8 @@ hw.module @Trivial(in %clock: !seq.clock, in %i0: i4, in %reset: i1, out out: i4

// CHECK-LABEL: hw.module @NonTrivial(
hw.module @NonTrivial(in %clock: !seq.clock, in %i0: i4, in %reset1: i1, in %reset2: i1, out out1: i4, out out2: i4) {
// CHECK: [[RES2:%.+]] = arc.state @[[NONTRIVIAL_ARC_0]](%i0) clock %clock reset %reset1 lat 1 {names = ["foo"]
// CHECK-NEXT: [[RES3:%.+]] = arc.state @[[NONTRIVIAL_ARC_1]](%i0) clock %clock reset %reset2 lat 1 {names = ["bar"]
// CHECK: [[RES2:%.+]] = arc.state @[[NONTRIVIAL_ARC_0]](%i0) clock %clock reset %reset1 latency 1 {names = ["foo"]
// CHECK-NEXT: [[RES3:%.+]] = arc.state @[[NONTRIVIAL_ARC_1]](%i0) clock %clock reset %reset2 latency 1 {names = ["bar"]
// CHECK-NEXT: hw.output [[RES2]], [[RES3]]
%0 = hw.constant 0 : i4
%foo = seq.compreg %i0, %clock reset %reset1, %0 : i4
Expand Down
2 changes: 1 addition & 1 deletion test/Dialect/Arc/Reduction/state-elimination.mlir
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Expand Up @@ -5,7 +5,7 @@
// CHECK-LABEL: hw.module @Foo
hw.module @Foo(in %clk: !seq.clock, in %en: i1, in %rst: i1, in %arg0: i32, out out: i32) {
// CHECK-NEXT: [[V0:%.+]] = arc.call @DummyArc(%arg0) : (i32) -> i32
%0 = arc.state @DummyArc(%arg0) clock %clk enable %en reset %rst lat 1 {name="reg1"} : (i32) -> (i32)
%0 = arc.state @DummyArc(%arg0) clock %clk enable %en reset %rst latency 1 {name="reg1"} : (i32) -> (i32)
// CHECK-NEXT: hw.output [[V0]]
hw.output %0 : i32
}
Expand Down
20 changes: 10 additions & 10 deletions test/Dialect/Arc/arc-canonicalizer.mlir
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Expand Up @@ -8,10 +8,10 @@
hw.module @passthoughChecks(in %clock: !seq.clock, in %in0: i1, in %in1: i1, out out0: i1, out out1: i1, out out2: i1, out out3: i1, out out4: i1, out out5: i1) {
%0:2 = arc.call @passthrough(%in0, %in1) : (i1, i1) -> (i1, i1)
%1:2 = arc.call @noPassthrough(%in0, %in1) : (i1, i1) -> (i1, i1)
%2:2 = arc.state @passthrough(%in0, %in1) clock %clock lat 1 : (i1, i1) -> (i1, i1)
%2:2 = arc.state @passthrough(%in0, %in1) clock %clock latency 1 : (i1, i1) -> (i1, i1)
hw.output %0#0, %0#1, %1#0, %1#1, %2#0, %2#1 : i1, i1, i1, i1, i1, i1
// CHECK-NEXT: [[V0:%.+]]:2 = arc.call @noPassthrough(%in0, %in1) :
// CHECK-NEXT: [[V2:%.+]]:2 = arc.state @passthrough(%in0, %in1) clock %clock lat 1 :
// CHECK-NEXT: [[V2:%.+]]:2 = arc.state @passthrough(%in0, %in1) clock %clock latency 1 :
// CHECK-NEXT: hw.output %in0, %in1, [[V0]]#0, [[V0]]#1, [[V2]]#0, [[V2]]#1 :
}
arc.define @passthrough(%arg0: i1, %arg1: i1) -> (i1, i1) {
Expand All @@ -38,11 +38,11 @@ arc.define @memArcTrue(%arg0: i1, %arg1: i32) -> (i1, i32, i1) {
hw.module @memoryWritePortCanonicalizations(in %clk: !seq.clock, in %addr: i1, in %data: i32) {
// CHECK-NEXT: [[MEM:%.+]] = arc.memory <2 x i32, i1>
%mem = arc.memory <2 x i32, i1>
arc.memory_write_port %mem, @memArcFalse(%addr, %data) clock %clk enable lat 1 : <2 x i32, i1>, i1, i32
// CHECK-NEXT: arc.memory_write_port [[MEM]], @memArcTrue_0(%addr, %data) clock %clk lat 1 :
arc.memory_write_port %mem, @memArcTrue(%addr, %data) clock %clk enable lat 1 : <2 x i32, i1>, i1, i32
// CHECK-NEXT: arc.memory_write_port [[MEM]], @memArcTrue_0(%addr, %data) clock %clk lat 1 :
arc.memory_write_port %mem, @memArcTrue(%addr, %data) clock %clk enable lat 1 : <2 x i32, i1>, i1, i32
arc.memory_write_port %mem, @memArcFalse(%addr, %data) clock %clk enable latency 1 : <2 x i32, i1>, i1, i32
// CHECK-NEXT: arc.memory_write_port [[MEM]], @memArcTrue_0(%addr, %data) clock %clk latency 1 :
arc.memory_write_port %mem, @memArcTrue(%addr, %data) clock %clk enable latency 1 : <2 x i32, i1>, i1, i32
// CHECK-NEXT: arc.memory_write_port [[MEM]], @memArcTrue_0(%addr, %data) clock %clk latency 1 :
arc.memory_write_port %mem, @memArcTrue(%addr, %data) clock %clk enable latency 1 : <2 x i32, i1>, i1, i32
// COM: trivially dead operation, requires listener callback to keep symbol cache up-to-date
%0:3 = arc.call @memArcTrue(%addr, %data) : (i1, i32) -> (i1, i32, i1)
// CHECK-NEXT: hw.output
Expand Down Expand Up @@ -149,10 +149,10 @@ arc.define @OneOfThreeUsed(%arg0: i1, %arg1: i1, %arg2: i1) -> i1 {

// CHECK: @test1
hw.module @test1 (in %arg0: i1, in %arg1: i1, in %arg2: i1, in %clock: !seq.clock, out out0: i1, out out1: i1) {
// CHECK-NEXT: arc.state @OneOfThreeUsed(%arg1) clock %clock lat 1 : (i1) -> i1
%0 = arc.state @OneOfThreeUsed(%arg0, %arg1, %arg2) clock %clock lat 1 : (i1, i1, i1) -> i1
// CHECK-NEXT: arc.state @OneOfThreeUsed(%arg1) clock %clock latency 1 : (i1) -> i1
%0 = arc.state @OneOfThreeUsed(%arg0, %arg1, %arg2) clock %clock latency 1 : (i1, i1, i1) -> i1
// CHECK-NEXT: arc.state @NestedCall(%arg1)
%1 = arc.state @NestedCall(%arg0, %arg1, %arg2) clock %clock lat 1 : (i1, i1, i1) -> i1
%1 = arc.state @NestedCall(%arg0, %arg1, %arg2) clock %clock latency 1 : (i1, i1, i1) -> i1
hw.output %0, %1 : i1, i1
}

Expand Down
16 changes: 8 additions & 8 deletions test/Dialect/Arc/basic-errors.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
// expected-error @+1 {{body contains non-pure operation}}
arc.define @Foo(%arg0: !seq.clock) {
// expected-note @+1 {{first non-pure operation here:}}
arc.state @Bar() clock %arg0 lat 1 : () -> ()
arc.state @Bar() clock %arg0 latency 1 : () -> ()
arc.output
}
arc.define @Bar() {
Expand All @@ -14,7 +14,7 @@ arc.define @Bar() {

hw.module @Foo(in %clock: !seq.clock) {
// expected-error @+1 {{'arc.state' op outside a clock domain requires a clock}}
arc.state @Bar() lat 1 : () -> ()
arc.state @Bar() latency 1 : () -> ()
}
arc.define @Bar() {
arc.output
Expand All @@ -24,7 +24,7 @@ arc.define @Bar() {

hw.module @Foo(in %clock: !seq.clock) {
// expected-error @+1 {{'arc.state' op latency must be a positive integer}}
arc.state @Bar() clock %clock lat 0 : () -> ()
arc.state @Bar() clock %clock latency 0 : () -> ()
}
arc.define @Bar() {
arc.output
Expand All @@ -36,7 +36,7 @@ arc.define @Bar() {
arc.define @SupportRecursiveMemoryEffects(%arg0: i1, %arg1: !seq.clock) {
// expected-note @+1 {{first non-pure operation here:}}
scf.if %arg0 {
arc.state @Bar() clock %arg1 lat 1 : () -> ()
arc.state @Bar() clock %arg1 latency 1 : () -> ()
}
arc.output
}
Expand Down Expand Up @@ -252,7 +252,7 @@ hw.module @stateOpInsideClockDomain(in %clk: !seq.clock) {
arc.clock_domain (%clk) clock %clk : (!seq.clock) -> () {
^bb0(%arg0: !seq.clock):
// expected-error @+1 {{inside a clock domain cannot have a clock}}
arc.state @dummyArc() clock %arg0 lat 1 : () -> ()
arc.state @dummyArc() clock %arg0 latency 1 : () -> ()
arc.output
}
hw.output
Expand All @@ -269,7 +269,7 @@ hw.module @memoryWritePortOpInsideClockDomain(in %clk: !seq.clock) {
%mem = arc.memory <4 x i32, i32>
%c0_i32 = hw.constant 0 : i32
// expected-error @+1 {{inside a clock domain cannot have a clock}}
arc.memory_write_port %mem, @identity(%c0_i32, %c0_i32, %arg0) clock %arg0 enable lat 1: !arc.memory<4 x i32, i32>, i32, i32, !seq.clock
arc.memory_write_port %mem, @identity(%c0_i32, %c0_i32, %arg0) clock %arg0 enable latency 1: !arc.memory<4 x i32, i32>, i32, i32, !seq.clock
arc.output
}
}
Expand All @@ -283,7 +283,7 @@ hw.module @memoryWritePortOpOutsideClockDomain(in %clock: !seq.clock, in %en: i1
%mem = arc.memory <4 x i32, i32>
%c0_i32 = hw.constant 0 : i32
// expected-error @+1 {{outside a clock domain requires a clock}}
arc.memory_write_port %mem, @identity(%c0_i32, %c0_i32, %en) lat 1 : !arc.memory<4 x i32, i32>, i32, i32, i1
arc.memory_write_port %mem, @identity(%c0_i32, %c0_i32, %en) latency 1 : !arc.memory<4 x i32, i32>, i32, i32, i1
}
arc.define @identity(%addr: i32, %data: i32, %enable: i1) -> (i32, i32, i1) {
arc.output %addr, %data, %enable : i32, i32, i1
Expand All @@ -295,7 +295,7 @@ hw.module @memoryWritePortOpLatZero(in %clock: !seq.clock, in %en: i1) {
%mem = arc.memory <4 x i32, i32>
%c0_i32 = hw.constant 0 : i32
// expected-error @+1 {{latency must be at least 1}}
arc.memory_write_port %mem, @identity(%c0_i32, %c0_i32, %en) lat 0 : !arc.memory<4 x i32, i32>, i32, i32, i1
arc.memory_write_port %mem, @identity(%c0_i32, %c0_i32, %en) latency 0 : !arc.memory<4 x i32, i32>, i32, i32, i1
}
arc.define @identity(%addr: i32, %data: i32, %enable: i1) -> (i32, i32, i1) {
arc.output %addr, %data, %enable : i32, i32, i1
Expand Down
36 changes: 18 additions & 18 deletions test/Dialect/Arc/basic.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -14,11 +14,11 @@ arc.define @Bar(%arg0: i42) -> i42 {

// CHECK-LABEL: hw.module @Module
hw.module @Module(in %clock: !seq.clock, in %enable: i1, in %a: i42, in %b: i9) {
// CHECK: arc.state @Foo(%a, %b) clock %clock lat 1 : (i42, i9) -> (i42, i9)
arc.state @Foo(%a, %b) clock %clock lat 1 : (i42, i9) -> (i42, i9)
// CHECK: arc.state @Foo(%a, %b) clock %clock latency 1 : (i42, i9) -> (i42, i9)
arc.state @Foo(%a, %b) clock %clock latency 1 : (i42, i9) -> (i42, i9)

// CHECK: arc.state @Foo(%a, %b) clock %clock enable %enable lat 1 : (i42, i9) -> (i42, i9)
arc.state @Foo(%a, %b) clock %clock enable %enable lat 1 : (i42, i9) -> (i42, i9)
// CHECK: arc.state @Foo(%a, %b) clock %clock enable %enable latency 1 : (i42, i9) -> (i42, i9)
arc.state @Foo(%a, %b) clock %clock enable %enable latency 1 : (i42, i9) -> (i42, i9)
}

// CHECK-LABEL: arc.define @SupportRecurisveMemoryEffects
Expand Down Expand Up @@ -115,14 +115,14 @@ hw.module @memoryOps(in %clk: !seq.clock, in %en: i1, in %mask: i32, in %arg: i1

// CHECK-NEXT: %{{.+}} = arc.memory_read_port [[MEM]][%c0_i32] : <4 x i32, i32>
%0 = arc.memory_read_port %mem[%c0_i32] : <4 x i32, i32>
// CHECK-NEXT: arc.memory_write_port [[MEM]], @identity1(%c0_i32, %c0_i32, %en) clock %clk enable lat 1 : <4 x i32, i32>, i32, i32, i1
arc.memory_write_port %mem, @identity1(%c0_i32, %c0_i32, %en) clock %clk enable lat 1 : <4 x i32, i32>, i32, i32, i1
// CHECK-NEXT: arc.memory_write_port [[MEM]], @identity2(%c0_i32, %c0_i32, %en, %mask) clock %clk enable mask lat 2 : <4 x i32, i32>, i32, i32, i1, i32
arc.memory_write_port %mem, @identity2(%c0_i32, %c0_i32, %en, %mask) clock %clk enable mask lat 2 : <4 x i32, i32>, i32, i32, i1, i32
// CHECK-NEXT: arc.memory_write_port [[MEM]], @identity3(%c0_i32, %c0_i32, %mask) clock %clk mask lat 3 : <4 x i32, i32>, i32, i32, i32
arc.memory_write_port %mem, @identity3(%c0_i32, %c0_i32, %mask) clock %clk mask lat 3 : <4 x i32, i32>, i32, i32, i32
// CHECK-NEXT: arc.memory_write_port [[MEM]], @identity(%c0_i32, %c0_i32) clock %clk lat 4 : <4 x i32, i32>, i32, i32
arc.memory_write_port %mem, @identity(%c0_i32, %c0_i32) clock %clk lat 4 : <4 x i32, i32>, i32, i32
// CHECK-NEXT: arc.memory_write_port [[MEM]], @identity1(%c0_i32, %c0_i32, %en) clock %clk enable latency 1 : <4 x i32, i32>, i32, i32, i1
arc.memory_write_port %mem, @identity1(%c0_i32, %c0_i32, %en) clock %clk enable latency 1 : <4 x i32, i32>, i32, i32, i1
// CHECK-NEXT: arc.memory_write_port [[MEM]], @identity2(%c0_i32, %c0_i32, %en, %mask) clock %clk enable mask latency 2 : <4 x i32, i32>, i32, i32, i1, i32
arc.memory_write_port %mem, @identity2(%c0_i32, %c0_i32, %en, %mask) clock %clk enable mask latency 2 : <4 x i32, i32>, i32, i32, i1, i32
// CHECK-NEXT: arc.memory_write_port [[MEM]], @identity3(%c0_i32, %c0_i32, %mask) clock %clk mask latency 3 : <4 x i32, i32>, i32, i32, i32
arc.memory_write_port %mem, @identity3(%c0_i32, %c0_i32, %mask) clock %clk mask latency 3 : <4 x i32, i32>, i32, i32, i32
// CHECK-NEXT: arc.memory_write_port [[MEM]], @identity(%c0_i32, %c0_i32) clock %clk latency 4 : <4 x i32, i32>, i32, i32
arc.memory_write_port %mem, @identity(%c0_i32, %c0_i32) clock %clk latency 4 : <4 x i32, i32>, i32, i32

// CHECK-NEXT: arc.clock_domain
arc.clock_domain (%arg) clock %clk : (i1) -> () {
Expand All @@ -132,10 +132,10 @@ hw.module @memoryOps(in %clk: !seq.clock, in %en: i1, in %mask: i32, in %arg: i1
%mem2 = arc.memory <4 x i32, i32>
// CHECK-NEXT: %{{.+}} = arc.memory_read_port [[MEM2]][%c1_i32] : <4 x i32, i32>
%2 = arc.memory_read_port %mem2[%c1_i32] : <4 x i32, i32>
// CHECK-NEXT: arc.memory_write_port [[MEM2]], @identity1(%c1_i32, %c1_i32, %arg0) enable lat 1 : <4 x i32, i32>, i32, i32, i1
arc.memory_write_port %mem2, @identity1(%c1_i32, %c1_i32, %arg0) enable lat 1 : <4 x i32, i32>, i32, i32, i1
// CHECK-NEXT: arc.memory_write_port [[MEM2]], @identity(%c1_i32, %c1_i32) lat 1 : <4 x i32, i32>, i32, i32
arc.memory_write_port %mem2, @identity(%c1_i32, %c1_i32) lat 1 : <4 x i32, i32>, i32, i32
// CHECK-NEXT: arc.memory_write_port [[MEM2]], @identity1(%c1_i32, %c1_i32, %arg0) enable latency 1 : <4 x i32, i32>, i32, i32, i1
arc.memory_write_port %mem2, @identity1(%c1_i32, %c1_i32, %arg0) enable latency 1 : <4 x i32, i32>, i32, i32, i1
// CHECK-NEXT: arc.memory_write_port [[MEM2]], @identity(%c1_i32, %c1_i32) latency 1 : <4 x i32, i32>, i32, i32
arc.memory_write_port %mem2, @identity(%c1_i32, %c1_i32) latency 1 : <4 x i32, i32>, i32, i32
}

// CHECK: %{{.+}} = arc.memory_read [[MEM]][%c0_i32] : <4 x i32, i32>
Expand Down Expand Up @@ -166,7 +166,7 @@ hw.module @vectorize_in_clock_domain(in %in0: i2, in %in1: i2, in %in2: i1, in %
^bb0(%arg0: i2, %arg1: i2, %arg2: i1, %arg3: i1):
%1:2 = arc.vectorize (%arg0, %arg1), (%arg2, %arg3) : (i2, i2, i1, i1) -> (i1, i1) {
^bb0(%arg4: i2, %arg5: i1):
%2 = arc.state @vectorizable(%arg4, %arg5) lat 1 : (i2, i1) -> i1
%2 = arc.state @vectorizable(%arg4, %arg5) latency 1 : (i2, i1) -> i1
arc.vectorize.return %2 : i1
}
arc.output %1#0, %1#1 : i1, i1
Expand All @@ -183,7 +183,7 @@ arc.define @vectorizable(%arg0: i2, %arg1: i1) -> i1 {
// CHECK: arc.clock_domain
// CHECK: %{{.+}}:2 = arc.vectorize ({{.*}}, {{.*}}), ({{.*}}, {{.*}}) : (i2, i2, i1, i1) -> (i1, i1) {
// CHECK: ^bb0([[A:%.+]]: i2, [[B:%.+]]: i1):
// CHECK: [[V1:%.+]] = arc.state @vectorizable([[A]], [[B]]) lat 1 : (i2, i1) -> i1
// CHECK: [[V1:%.+]] = arc.state @vectorizable([[A]], [[B]]) latency 1 : (i2, i1) -> i1
// CHECK: arc.vectorize.return [[V1]] : i1
// CHECK: }

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