[ExportVerilog] Drop external module emission #7558
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Stop emitting external modules entirely in single file emission and drop the creation of "extern_modules.sv" in split file emission. This is done because it creates problems/confusion for Verilog generation flows which are trying to hide the existence of some modules. E.g., the existence of "extern_modules.sv" will leak what external modules were instantiated under a FIRRTL layerblock. Alternatively, this could be revived by creating these files by respecting the output file attributes on external modules such that each significant directory got such a file. Signed-off-by: Schuyler Eldridge <[email protected]>
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Stop emitting external modules entirely in single file emission and drop the creation of "extern_modules.sv" in split file emission. This is done because it creates problems/confusion for Verilog generation flows which are trying to hide the existence of some modules. E.g., the existence of "extern_modules.sv" will leak what external modules were instantiated under a FIRRTL layerblock.
Alternatively, this could be revived by creating these files by respecting the output file attributes on external modules such that each significant directory got such a file.