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Use 4-byte spill size in case of no vector support.
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@JonPsson1
JonPsson1 committed Dec 5, 2024
1 parent 3e31dce commit 8932f4a
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Showing 14 changed files with 87 additions and 109 deletions.
2 changes: 2 additions & 0 deletions llvm/lib/Target/SystemZ/SystemZFeatures.td
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Expand Up @@ -196,6 +196,8 @@ def FeatureVector : SystemZFeature<
>;
def FeatureNoVector : SystemZMissingFeature<"Vector">;

def NoVecHwMode : HwMode<"-vector", [FeatureNoVector]>;

def Arch11NewFeatures : SystemZFeatureList<[
FeatureLoadAndZeroRightmostByte,
FeatureLoadStoreOnCond2,
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6 changes: 6 additions & 0 deletions llvm/lib/Target/SystemZ/SystemZInstrFP.td
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Expand Up @@ -134,6 +134,9 @@ defm LoadStoreF128 : MVCLoadStore<load, f128, MVCImm, 15>;
//===----------------------------------------------------------------------===//

let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in {
let isCodeGenOnly = 1 in
// Reload f16 from 4-byte spill slot.
defm LE16 : UnaryRXPair<"le", 0x78, 0xED64, z_load, FP16, 4>;
defm LE : UnaryRXPair<"le", 0x78, 0xED64, z_load, FP32, 4>;
defm LD : UnaryRXPair<"ld", 0x68, 0xED65, z_load, FP64, 8>;

Expand All @@ -154,6 +157,9 @@ let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in {
//===----------------------------------------------------------------------===//

let SimpleBDXStore = 1, mayStore = 1 in {
let isCodeGenOnly = 1 in
// Spill f16 to 4-byte spill slot.
defm STE16 : StoreRXPair<"ste", 0x70, 0xED66, store, FP16, 4>;
defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>;
defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>;

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59 changes: 9 additions & 50 deletions llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
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Expand Up @@ -61,7 +61,8 @@ void SystemZInstrInfo::anchor() {}

SystemZInstrInfo::SystemZInstrInfo(SystemZSubtarget &sti)
: SystemZGenInstrInfo(-1, -1),
RI(sti.getSpecialRegisters()->getReturnFunctionAddressRegister()),
RI(sti.getSpecialRegisters()->getReturnFunctionAddressRegister(),
sti.getHwMode()),
STI(sti) {}

// MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
Expand Down Expand Up @@ -996,31 +997,8 @@ void SystemZInstrInfo::storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
bool isKill, int FrameIdx, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI, Register VReg) const {
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();

// Without vector support, there are no fp16 load/store instructions, so
// need to save/restore via GPR.
if (RC == &SystemZ::FP16BitRegClass && !STI.hasVector()) {
assert(!MRI.isSSA() && MRI.getNumVirtRegs() &&
"Expected non-SSA form with virtual registers.");
Register GR64Reg = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
Register FP64Reg = MRI.createVirtualRegister(&SystemZ::FP64BitRegClass);
BuildMI(MBB, MBBI, DL, get(SystemZ::COPY))
.addReg(FP64Reg, RegState::DefineNoRead, SystemZ::subreg_h16)
.addReg(SrcReg, getKillRegState(isKill));
BuildMI(MBB, MBBI, DL, get(SystemZ::LGDR), GR64Reg)
.addReg(FP64Reg, RegState::Kill);
BuildMI(MBB, MBBI, DL, get(SystemZ::SRLG), GR64Reg)
.addReg(GR64Reg)
.addReg(0)
.addImm(48);
addFrameReference(BuildMI(MBB, MBBI, DL, get(SystemZ::STH))
.addReg(GR64Reg, RegState::Kill, SystemZ::subreg_l32),
FrameIdx);
return;
}

// Callers may expect a single instruction, so keep 128-bit moves
// together for now and lower them after register allocation.
unsigned LoadOpcode, StoreOpcode;
Expand All @@ -1036,31 +1014,8 @@ void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
Register VReg) const {
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();

// Without vector support, there are no fp16 load/store instructions, so
// need to save/restore via GPR.
if (RC == &SystemZ::FP16BitRegClass && !STI.hasVector()) {
assert(!MRI.isSSA() && MRI.getNumVirtRegs() &&
"Expected non-SSA form with virtual registers.");
Register GR64Reg = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
Register FP64Reg = MRI.createVirtualRegister(&SystemZ::FP64BitRegClass);
addFrameReference(
BuildMI(MBB, MBBI, DL, get(SystemZ::LH))
.addReg(GR64Reg, RegState::DefineNoRead, SystemZ::subreg_l32),
FrameIdx);
BuildMI(MBB, MBBI, DL, get(SystemZ::SLLG), GR64Reg)
.addReg(GR64Reg)
.addReg(0)
.addImm(48);
BuildMI(MBB, MBBI, DL, get(SystemZ::LDGR), FP64Reg)
.addReg(GR64Reg, RegState::Kill);
BuildMI(MBB, MBBI, DL, get(SystemZ::COPY), DestReg)
.addReg(FP64Reg, RegState::Kill, SystemZ::subreg_h16);
return;
}

// Callers may expect a single instruction, so keep 128-bit moves
// together for now and lower them after register allocation.
unsigned LoadOpcode, StoreOpcode;
Expand Down Expand Up @@ -1281,9 +1236,10 @@ MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
return nullptr;

unsigned OpNum = Ops[0];
assert(Size * 8 ==
TRI->getRegSizeInBits(*MF.getRegInfo()
.getRegClass(MI.getOperand(OpNum).getReg())) &&
const TargetRegisterClass *RC =
MF.getRegInfo().getRegClass(MI.getOperand(OpNum).getReg());
assert((Size * 8 == TRI->getRegSizeInBits(*RC) ||
(RC == &SystemZ::FP16BitRegClass && Size == 4 && !STI.hasVector())) &&
"Invalid size combination");

if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
Expand Down Expand Up @@ -1922,6 +1878,9 @@ void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
RC == &SystemZ::ADDR128BitRegClass) {
LoadOpcode = SystemZ::L128;
StoreOpcode = SystemZ::ST128;
} else if (RC == &SystemZ::FP16BitRegClass && !STI.hasVector()) {
LoadOpcode = SystemZ::LE16;
StoreOpcode = SystemZ::STE16;
} else if (RC == &SystemZ::FP32BitRegClass) {
LoadOpcode = SystemZ::LE;
StoreOpcode = SystemZ::STE;
Expand Down
5 changes: 3 additions & 2 deletions llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
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Expand Up @@ -233,8 +233,9 @@ SystemZELFRegisters::getCallPreservedMask(const MachineFunction &MF,
return CSR_SystemZ_ELF_RegMask;
}

SystemZRegisterInfo::SystemZRegisterInfo(unsigned int RA)
: SystemZGenRegisterInfo(RA) {}
SystemZRegisterInfo::SystemZRegisterInfo(unsigned int RA, unsigned int HwMode)
: SystemZGenRegisterInfo(RA, /*DwarfFlavour=*/0, /*EHFlavour=*/0, /*PC=*/0,
HwMode) {}

const MCPhysReg *
SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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2 changes: 1 addition & 1 deletion llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
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Expand Up @@ -129,7 +129,7 @@ class SystemZELFRegisters : public SystemZCallingConventionRegisters {

struct SystemZRegisterInfo : public SystemZGenRegisterInfo {
public:
SystemZRegisterInfo(unsigned int RA);
SystemZRegisterInfo(unsigned int RA, unsigned int HwMode);

/// getPointerRegClass - Return the register class to use to hold pointers.
/// This is currently only used by LOAD_STACK_GUARD, which requires a non-%r0
Expand Down
11 changes: 9 additions & 2 deletions llvm/lib/Target/SystemZ/SystemZRegisterInfo.td
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Expand Up @@ -35,7 +35,9 @@ def subreg_ll32 : ComposedSubRegIndex<subreg_l64, subreg_l32>;
// If the user provides an alternate order list of regs, it will be used for
// XPLINK. Otherwise, by default, XPLINK will use the regList ordering as well
multiclass SystemZRegClass<string name, list<ValueType> types, int size,
dag regList, list<dag> altRegList = [regList], bit allocatable = 1> {
dag regList, list<dag> altRegList = [regList],
bit allocatable = 1,
RegInfoByHwMode RI = RegInfoByHwMode<[], []>> {
def AsmOperand : AsmOperandClass {
let Name = name;
let ParserMethod = "parse"#name;
Expand All @@ -49,6 +51,7 @@ multiclass SystemZRegClass<string name, list<ValueType> types, int size,
const SystemZSubtarget &S = MF.getSubtarget<SystemZSubtarget>();
return S.isTargetXPLINK64();
}];
let RegInfos = RI;
}
def "" : RegisterOperand<!cast<RegisterClass>(name#"Bit")> {
let ParserMatchClass = !cast<AsmOperandClass>(name#"AsmOperand");
Expand Down Expand Up @@ -250,7 +253,11 @@ foreach I = [0, 1, 4, 5, 8, 9, 12, 13] in {

// There's no store-multiple instruction for FPRs, so we're not fussy
// about the order in which call-saved registers are allocated.
defm FP16 : SystemZRegClass<"FP16", [f16], 16, (sequence "F%uH", 0, 15)>;
// Adjust the spill size of f16 to 32 bits in case of no vector support.
def FP16RI : RegInfoByHwMode<[DefaultMode, NoVecHwMode],
[RegInfo<16,16,16>, RegInfo<16,32,32>]>;
defm FP16 : SystemZRegClass<"FP16", [f16], 16, (sequence "F%uH", 0, 15),
[(sequence "F%uH", 0, 15)], 1, FP16RI>;
defm FP32 : SystemZRegClass<"FP32", [f32], 32, (sequence "F%uS", 0, 15)>;
defm FP64 : SystemZRegClass<"FP64", [f64], 64, (sequence "F%uD", 0, 15)>;
defm FP128 : SystemZRegClass<"FP128", [f128], 128,
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
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Expand Up @@ -793,15 +793,15 @@ def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "CPSDR(d|s)(d|s)$")>;
// FP: Load instructions
//===----------------------------------------------------------------------===//

def : InstRW<[WLat2LSU, VecXsPm, LSU, NormalGr], (instregex "LE(Y)?$")>;
def : InstRW<[WLat2LSU, VecXsPm, LSU, NormalGr], (instregex "L(E16|E)(Y)?$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LD(Y|E32)?$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LX$")>;

//===----------------------------------------------------------------------===//
// FP: Store instructions
//===----------------------------------------------------------------------===//

def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(E|D)(Y)?$")>;
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(E16|E|D)(Y)?$")>;
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STX$")>;

//===----------------------------------------------------------------------===//
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
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Expand Up @@ -813,15 +813,15 @@ def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "CPSDR(d|s)(d|s)$")>;
// FP: Load instructions
//===----------------------------------------------------------------------===//

def : InstRW<[WLat2LSU, VecXsPm, LSU, NormalGr], (instregex "LE(Y)?$")>;
def : InstRW<[WLat2LSU, VecXsPm, LSU, NormalGr], (instregex "L(E16|E)(Y)?$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LD(Y|E32)?$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LX$")>;

//===----------------------------------------------------------------------===//
// FP: Store instructions
//===----------------------------------------------------------------------===//

def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(E|D)(Y)?$")>;
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(E16|E|D)(Y)?$")>;
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STX$")>;

//===----------------------------------------------------------------------===//
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
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Expand Up @@ -831,15 +831,15 @@ def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "CPSDR(d|s)(d|s)$")>;
// FP: Load instructions
//===----------------------------------------------------------------------===//

def : InstRW<[WLat2LSU, VecXsPm, LSU, NormalGr], (instregex "LE(Y)?$")>;
def : InstRW<[WLat2LSU, VecXsPm, LSU, NormalGr], (instregex "L(E16|E)(Y)?$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LD(Y|E32)?$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LX$")>;

//===----------------------------------------------------------------------===//
// FP: Store instructions
//===----------------------------------------------------------------------===//

def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(E|D)(Y)?$")>;
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(E16|E|D)(Y)?$")>;
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STX$")>;

//===----------------------------------------------------------------------===//
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
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Original file line number Diff line number Diff line change
Expand Up @@ -832,15 +832,15 @@ def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "CPSDR(d|s)(d|s)$")>;
// FP: Load instructions
//===----------------------------------------------------------------------===//

def : InstRW<[WLat2LSU, VecXsPm, LSU, NormalGr], (instregex "LE(Y)?$")>;
def : InstRW<[WLat2LSU, VecXsPm, LSU, NormalGr], (instregex "L(E16|E)(Y)?$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LD(Y|E32)?$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LX$")>;

//===----------------------------------------------------------------------===//
// FP: Store instructions
//===----------------------------------------------------------------------===//

def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(E|D)(Y)?$")>;
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "ST(E16|E|D)(Y)?$")>;
def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STX$")>;

//===----------------------------------------------------------------------===//
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
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Expand Up @@ -725,14 +725,14 @@ def : InstRW<[WLat5, FXU2, GroupAlone], (instregex "CPSDR(d|s)(d|s)$")>;
// FP: Load instructions
//===----------------------------------------------------------------------===//

def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(E|D)(Y|E32)?$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(E16|E|D)(Y|E32)?$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LX$")>;

//===----------------------------------------------------------------------===//
// FP: Store instructions
//===----------------------------------------------------------------------===//

def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST(E|D)(Y)?$")>;
def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST(E16|E|D)(Y)?$")>;
def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STX$")>;

//===----------------------------------------------------------------------===//
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
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Original file line number Diff line number Diff line change
Expand Up @@ -763,14 +763,14 @@ def : InstRW<[WLat5, FXU2, GroupAlone], (instregex "CPSDR(d|s)(d|s)$")>;
// FP: Load instructions
//===----------------------------------------------------------------------===//

def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(E|D)(Y|E32)?$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(E16|E|D)(Y|E32)?$")>;
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LX$")>;

//===----------------------------------------------------------------------===//
// FP: Store instructions
//===----------------------------------------------------------------------===//

def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST(E|D)(Y)?$")>;
def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST(E16|E|D)(Y)?$")>;
def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STX$")>;

//===----------------------------------------------------------------------===//
Expand Down
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