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[mlir][vector][print] do not append newline to printing pure strings (#…
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…83213)

Since the vector.print str provides no punctuation control, it is
slightly more flexible to let the client of this operation decide
whether there should be a trailing newline. This allows for printing
like

vector.print str "nse = "
vector.print %nse : index

as

nse = 42
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@aartbik
aartbik authored Feb 28, 2024
1 parent 1c211bc commit c1b8c6c
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Showing 17 changed files with 66 additions and 65 deletions.
3 changes: 2 additions & 1 deletion mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
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Expand Up @@ -1532,7 +1532,8 @@ class VectorPrintOpConversion : public ConvertOpToLLVMPattern<vector::PrintOp> {
auto punct = printOp.getPunctuation();
if (auto stringLiteral = printOp.getStringLiteral()) {
LLVM::createPrintStrCall(rewriter, loc, parent, "vector_print_str",
*stringLiteral, *getTypeConverter());
*stringLiteral, *getTypeConverter(),
/*addNewline=*/false);
} else if (punct != PrintPunctuation::NoPunctuation) {
emitCall(rewriter, printOp->getLoc(), [&] {
switch (punct) {
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2 changes: 1 addition & 1 deletion mlir/test/Integration/Dialect/Arith/CPU/test-wide-int-emulation-compare-results-i16.mlir
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Expand Up @@ -26,7 +26,7 @@ func.func @check_results(%lhs : i16, %rhs : i16, %res0 : i16, %res1 : i16) -> ()
%mismatch = arith.cmpi ne, %res0, %res1 : i16
scf.if %mismatch -> () {
vector.print %res1 : i16
vector.print str "Mismatch"
vector.print str "Mismatch\n"
}
return
}
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2 changes: 1 addition & 1 deletion mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/fill-2d.mlir
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Expand Up @@ -88,7 +88,7 @@ func.func @entry() {
}

// CHECK: SME: END OF TEST OUTPUT
vector.print str "SME: END OF TEST OUTPUT"
vector.print str "SME: END OF TEST OUTPUT\n"

return
}
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10 changes: 5 additions & 5 deletions mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/use-too-many-tiles.mlir
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Expand Up @@ -24,23 +24,23 @@ func.func @use_too_many_tiles(%a: memref<?x?xi16>, %b: memref<?x?xi16>, %c: mem

// CHECK-LABEL: tile_a:
// CHECK-COUNT-8: ( 0, 0, 0, 0, 0, 0, 0, 0
vector.print str "tile_a:"
vector.print str "tile_a:\n"
vector.print %tile_a : vector<[8]x[8]xi16>
// CHECK-LABEL: tile_b:
// CHECK-COUNT-8: ( 1, 1, 1, 1, 1, 1, 1, 1
vector.print str "tile_b:"
vector.print str "tile_b:\n"
vector.print %tile_b : vector<[8]x[8]xi16>
// CHECK-LABEL: tile_c:
// CHECK-COUNT-8: ( 2, 2, 2, 2, 2, 2, 2, 2
vector.print str "tile_c:"
vector.print str "tile_c:\n"
vector.print %tile_c : vector<[8]x[8]xi16>
// CHECK-LABEL: tile_d:
// CHECK-COUNT-8: ( 3, 3, 3, 3, 3, 3, 3, 3
vector.print str "tile_d:"
vector.print str "tile_d:\n"
vector.print %tile_d : vector<[8]x[8]xi16>
// CHECK-LABEL: tile_e:
// CHECK-COUNT-8: ( 4, 4, 4, 4, 4, 4, 4, 4
vector.print str "tile_e:"
vector.print str "tile_e:\n"
vector.print %tile_e : vector<[8]x[8]xi16>
return
}
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8 changes: 4 additions & 4 deletions mlir/test/Integration/Dialect/Vector/CPU/ArmSME/Emulated/test-setArmSVLBits.mlir
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Expand Up @@ -12,13 +12,13 @@ func.func @checkSVL() {
%svl_h = arm_sme.streaming_vl <half>
%svl_w = arm_sme.streaming_vl <word>
%svl_d = arm_sme.streaming_vl <double>
vector.print str "SVL.b"
vector.print str "SVL.b\n"
vector.print %svl_b : index
vector.print str "SVL.h"
vector.print str "SVL.h\n"
vector.print %svl_h : index
vector.print str "SVL.w"
vector.print str "SVL.w\n"
vector.print %svl_w : index
vector.print str "SVL.d"
vector.print str "SVL.d\n"
vector.print %svl_d : index
return
}
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8 changes: 4 additions & 4 deletions mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-store-128-bit-tile.mlir
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Expand Up @@ -53,13 +53,13 @@ func.func @test_load_store_zaq0() {

// CHECK-LABEL: INITIAL TILE A:
// CHECK: ( 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 )
vector.print str "INITIAL TILE A:"
vector.print str "INITIAL TILE A:\n"
func.call @print_i8s(%tile_a_bytes, %zaq_size_bytes) : (memref<?xi8>, index) -> ()
vector.print punctuation <newline>

// CHECK-LABEL: INITIAL TILE B:
// CHECK: ( 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64 )
vector.print str "INITIAL TILE B:"
vector.print str "INITIAL TILE B:\n"
func.call @print_i8s(%tile_b_bytes, %zaq_size_bytes) : (memref<?xi8>, index) -> ()
vector.print punctuation <newline>

Expand All @@ -68,13 +68,13 @@ func.func @test_load_store_zaq0() {

// CHECK-LABEL: FINAL TILE A:
// CHECK: ( 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 )
vector.print str "FINAL TILE A:"
vector.print str "FINAL TILE A:\n"
func.call @print_i8s(%tile_a_bytes, %zaq_size_bytes) : (memref<?xi8>, index) -> ()
vector.print punctuation <newline>

// CHECK-LABEL: FINAL TILE B:
// CHECK: ( 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 )
vector.print str "FINAL TILE B:"
vector.print str "FINAL TILE B:\n"
func.call @print_i8s(%tile_b_bytes, %zaq_size_bytes) : (memref<?xi8>, index) -> ()

return
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8 changes: 4 additions & 4 deletions mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-load-vertical.mlir
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Expand Up @@ -49,12 +49,12 @@ func.func @entry() {
// CHECK-NEXT: ( 2, 2, 2, 2
// CHECK-NEXT: ( 3, 3, 3, 3
// CHECK: TILE END
vector.print str "TILE BEGIN"
vector.print str "TILE BEGIN\n"
scf.for %i = %c0 to %za_s_size step %svl_s {
%tileslice = vector.load %mem1[%i] : memref<?xi32>, vector<[4]xi32>
vector.print %tileslice : vector<[4]xi32>
}
vector.print str "TILE END"
vector.print str "TILE END\n"

// 2. VERTICAL LAYOUT
// Dump "mem2". The smallest SVL is 128-bits so the tile will be at least
Expand All @@ -66,9 +66,9 @@ func.func @entry() {
// CHECK-NEXT: ( 0, 1, 2, 3
// CHECK-NEXT: ( 0, 1, 2, 3
// CHECK: TILE END
vector.print str "TILE BEGIN"
vector.print str "TILE BEGIN\n"
vector.print %0 : vector<[4]x[4]xi32>
vector.print str "TILE END"
vector.print str "TILE END\n"

return
}
8 changes: 4 additions & 4 deletions mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-multi-tile-transpose.mlir
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Expand Up @@ -46,12 +46,12 @@ func.func @testTransposedReadWithMask(%maskRows: index, %maskCols: index) {
vector.transfer_write %readTransposed, %outDyn[%c0, %c0] {in_bounds = [true, true]} : vector<[16]x[4]xf32>, memref<?x?xf32>

/// Print the input memref.
vector.print str "Input memref:"
vector.print str "Input memref:\n"
%inUnranked = memref.cast %inDyn : memref<?x?xf32> to memref<*xf32>
call @printMemrefF32(%inUnranked) : (memref<*xf32>) -> ()

/// Print the result memref.
vector.print str "Masked transposed result:"
vector.print str "Masked transposed result:\n"
%outUnranked = memref.cast %outDyn : memref<?x?xf32> to memref<*xf32>
call @printMemrefF32(%outUnranked) : (memref<*xf32>) -> ()

Expand Down Expand Up @@ -84,12 +84,12 @@ func.func @testTransposedWriteWithMask(%maskRows: index, %maskCols: index) {
: vector<[16]x[4]xf32>, memref<?x?xf32>

/// Print the input memref.
vector.print str "Input memref:"
vector.print str "Input memref:\n"
%inUnranked = memref.cast %inDyn : memref<?x?xf32> to memref<*xf32>
call @printMemrefF32(%inUnranked) : (memref<*xf32>) -> ()

/// Print the result memref.
vector.print str "Masked transposed result:"
vector.print str "Masked transposed result:\n"
%outUnranked = memref.cast %outDyn : memref<?x?xf32> to memref<*xf32>
call @printMemrefF32(%outUnranked) : (memref<*xf32>) -> ()

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16 changes: 8 additions & 8 deletions mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-f32.mlir
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Expand Up @@ -35,9 +35,9 @@ func.func @test_outerproduct_no_accumulator_4x4xf32() {
// WITHOUT-ACC-NEXT: ( 0, 2, 4, 6
// WITHOUT-ACC-NEXT: ( 0, 3, 6, 9
// WITHOUT-ACC: TILE END
vector.print str "TILE BEGIN"
vector.print str "TILE BEGIN\n"
vector.print %tile : vector<[4]x[4]xf32>
vector.print str "TILE END"
vector.print str "TILE END\n"

return
}
Expand All @@ -60,9 +60,9 @@ func.func @test_outerproduct_with_accumulator_4x4xf32() {
// WITH-ACC-NEXT: ( 10, 12, 14, 16
// WITH-ACC-NEXT: ( 10, 13, 16, 19
// WITH-ACC: TILE END
vector.print str "TILE BEGIN"
vector.print str "TILE BEGIN\n"
vector.print %tile : vector<[4]x[4]xf32>
vector.print str "TILE END"
vector.print str "TILE END\n"

return
}
Expand Down Expand Up @@ -91,9 +91,9 @@ func.func @test_masked_outerproduct_no_accumulator_4x4xf32() {
// WITH-MASK-NEXT: ( 3, 6, 0, 0
// WITH-MASK-NEXT: ( 0, 0, 0, 0
// WITH-MASK: TILE END
vector.print str "TILE BEGIN"
vector.print str "TILE BEGIN\n"
vector.print %tile : vector<[4]x[4]xf32>
vector.print str "TILE END"
vector.print str "TILE END\n"

return
}
Expand Down Expand Up @@ -124,9 +124,9 @@ func.func @test_masked_outerproduct_with_accumulator_4x4xf32() {
// WITH-MASK-AND-ACC-NEXT: ( 10, 10, 10, 10
// WITH-MASK-AND-ACC-NEXT: ( 10, 10, 10, 10
// WITH-MASK-AND-ACC: TILE END
vector.print str "TILE BEGIN"
vector.print str "TILE BEGIN\n"
vector.print %tile : vector<[4]x[4]xf32>
vector.print str "TILE END"
vector.print str "TILE END\n"

return
}
16 changes: 8 additions & 8 deletions mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-f64.mlir
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Expand Up @@ -40,9 +40,9 @@ func.func @test_outerproduct_no_accumulator_2x2xf64() {
// CHECK-NEXT: ( 1, 2
// CHECK-NEXT: ( 2, 4
// CHECK: TILE END
vector.print str "TILE BEGIN"
vector.print str "TILE BEGIN\n"
vector.print %tile : vector<[2]x[2]xf64>
vector.print str "TILE END"
vector.print str "TILE END\n"

return
}
Expand All @@ -66,9 +66,9 @@ func.func @test_outerproduct_with_accumulator_2x2xf64() {
// WITH-ACC-NEXT: ( 11, 12
// WITH-ACC-NEXT: ( 12, 14
// WITH-ACC: TILE END
vector.print str "TILE BEGIN"
vector.print str "TILE BEGIN\n"
vector.print %tile : vector<[2]x[2]xf64>
vector.print str "TILE END"
vector.print str "TILE END\n"

return
}
Expand Down Expand Up @@ -96,9 +96,9 @@ func.func @test_masked_outerproduct_no_accumulator_2x2xf64() {
// WITH-MASK-NEXT: ( 1, 0
// WITH-MASK-NEXT: ( 2, 0
// WITH-MASK: TILE END
vector.print str "TILE BEGIN"
vector.print str "TILE BEGIN\n"
vector.print %tile : vector<[2]x[2]xf64>
vector.print str "TILE END"
vector.print str "TILE END\n"

return
}
Expand Down Expand Up @@ -127,9 +127,9 @@ func.func @test_masked_outerproduct_with_accumulator_2x2xf64() {
// WITH-MASK-AND-ACC-NEXT: ( 11, 12
// WITH-MASK-AND-ACC-NEXT: ( 10, 10
// WITH-MASK-AND-ACC: TILE END
vector.print str "TILE BEGIN"
vector.print str "TILE BEGIN\n"
vector.print %tile : vector<[2]x[2]xf64>
vector.print str "TILE END"
vector.print str "TILE END\n"

return
}
12 changes: 6 additions & 6 deletions mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-read-2d.mlir
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Expand Up @@ -14,7 +14,7 @@ func.func @transfer_read_2d(%A : memref<?x?xf32>, %base1: index, %base2: index)
%0 = vector.transfer_read %A[%base1, %base2], %pad {in_bounds=[true, true]} :
memref<?x?xf32>, vector<[4]x[4]xf32>

vector.print str "TILE BEGIN:"
vector.print str "TILE BEGIN:\n"
vector.print %0: vector<[4]x[4]xf32>

return
Expand All @@ -27,7 +27,7 @@ func.func @transfer_read_2d_transposed(%A : memref<?x?xf32>, %base1: index, %bas
{permutation_map = affine_map<(d0, d1) -> (d1, d0)>, in_bounds=[true, true]}
: memref<?x?xf32>, vector<[4]x[4]xf32>

vector.print str "TILE BEGIN:"
vector.print str "TILE BEGIN:\n"
vector.print %0 : vector<[4]x[4]xf32>

return
Expand All @@ -42,7 +42,7 @@ func.func @transfer_read_2d_mask(%A : memref<?x?xf32>, %base1: index, %base2: in
%0 = vector.transfer_read %A[%base1, %base2], %pad, %mask
{in_bounds = [true, true]} : memref<?x?xf32>, vector<[4]x[4]xf32>

vector.print str "TILE BEGIN:"
vector.print str "TILE BEGIN:\n"
vector.print %0: vector<[4]x[4]xf32>

return
Expand All @@ -58,7 +58,7 @@ func.func @transfer_read_2d_mask_transposed(%A : memref<?x?xf32>, %base1: index,
{permutation_map = affine_map<(d0, d1) -> (d1, d0)>, in_bounds=[true, true]}
: memref<?x?xf32>, vector<[4]x[4]xf32>

vector.print str "TILE BEGIN:"
vector.print str "TILE BEGIN:\n"
vector.print %0: vector<[4]x[4]xf32>

return
Expand All @@ -73,7 +73,7 @@ func.func @transfer_read_2d_mask_non_zero_pad(%A : memref<?x?xf32>, %base1: inde
%0 = vector.transfer_read %A[%base1, %base2], %pad, %mask
{in_bounds = [true, true]} : memref<?x?xf32>, vector<[4]x[4]xf32>

vector.print str "TILE BEGIN:"
vector.print str "TILE BEGIN:\n"
vector.print %0: vector<[4]x[4]xf32>

return
Expand All @@ -89,7 +89,7 @@ func.func @transfer_read_2d_mask_non_zero_pad_transposed(%A : memref<?x?xf32>, %
{permutation_map = affine_map<(d0, d1) -> (d1, d0)>, in_bounds=[true, true]}
: memref<?x?xf32>, vector<[4]x[4]xf32>

vector.print str "TILE BEGIN:"
vector.print str "TILE BEGIN:\n"
vector.print %0: vector<[4]x[4]xf32>

return
Expand Down
2 changes: 1 addition & 1 deletion mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-write-2d.mlir
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Expand Up @@ -51,7 +51,7 @@ func.func @transfer_write_2d_mask_transposed(%A : memref<?x?xf32>, %base1: index
func.func @load_and_print(%A : memref<?x?xf32>, %base1: index, %base2: index) {
%0 = vector.load %A[%base1, %base2] : memref<?x?xf32>, vector<[4]x[4]xf32>

vector.print str "TILE BEGIN:"
vector.print str "TILE BEGIN:\n"
vector.print %0: vector<[4]x[4]xf32>

return
Expand Down
8 changes: 4 additions & 4 deletions mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transpose.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -51,9 +51,9 @@ func.func @entry() {
// CHECK-NEXT: ( 2, 2, 2, 2
// CHECK-NEXT: ( 3, 3, 3, 3
// CHECK: TILE END
vector.print str "TILE BEGIN"
vector.print str "TILE BEGIN\n"
vector.print %tile : vector<[4]x[4]xi32>
vector.print str "TILE END"
vector.print str "TILE END\n"

// Dump the transposed tile. The smallest SVL is 128-bits so the tile will be
// at least 4x4xi32.
Expand All @@ -64,9 +64,9 @@ func.func @entry() {
// CHECK-NEXT: ( 0, 1, 2, 3
// CHECK-NEXT: ( 0, 1, 2, 3
// CHECK: TILE END
vector.print str "TILE BEGIN"
vector.print str "TILE BEGIN\n"
vector.print %transposed_tile : vector<[4]x[4]xi32>
vector.print str "TILE END"
vector.print str "TILE END\n"

return
}
4 changes: 2 additions & 2 deletions mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile_fill.mlir
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Expand Up @@ -23,9 +23,9 @@ func.func @entry() -> i32 {
// CHECK-NEXT: ( 123, 123, 123, 123
// CHECK-NEXT: ( 123, 123, 123, 123
// CHECK: TILE END
vector.print str "TILE BEGIN"
vector.print str "TILE BEGIN\n"
vector.print %tile : vector<[4]x[4]xi32>
vector.print str "TILE END"
vector.print str "TILE END\n"

%c0_i32 = arith.constant 0 : i32
return %c0_i32 : i32
Expand Down
8 changes: 4 additions & 4 deletions mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir
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Expand Up @@ -255,19 +255,19 @@ func.func @load_store_two_za_s_tiles() -> i32 {
// CHECK-NEXT: ( 1, 1, 1, 1
// CHECK-NEXT: ( 1, 1, 1, 1
// CHECK: TILE END
vector.print str "TILE BEGIN"
vector.print str "TILE BEGIN\n"
scf.for %i = %c0 to %size_of_two_tiles step %svl_s {
%av = vector.load %mem2[%i] : memref<?xi32>, vector<[4]xi32>
vector.print %av : vector<[4]xi32>

%tileSizeMinusStep = arith.subi %size_of_tile, %svl_s : index
%isNextTile = arith.cmpi eq, %i, %tileSizeMinusStep : index
scf.if %isNextTile {
vector.print str "TILE END"
vector.print str "TILE BEGIN"
vector.print str "TILE END\n"
vector.print str "TILE BEGIN\n"
}
}
vector.print str "TILE END"
vector.print str "TILE END\n"

return %c0_i32 : i32
}
Expand Down
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