AMDGPU: Fix missing functions in MIR tests

This function was in the IR section, but not present in the MIR function list.
llvm · Sep 24, 2024 · cde7b30 · cde7b30
1 parent fa089b0
commit cde7b30
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Showing 2 changed files with 39 additions and 4 deletions.
diff --git a/llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir b/llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
@@ -894,6 +894,42 @@ body:             |
     S_ENDPGM 0, implicit $agpr0
 ...
 
+---
+name:            a2_to_a2
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $agpr0_agpr1
+    ; GFX908-LABEL: name: a2_to_a2
+    ; GFX908: liveins: $agpr0_agpr1
+    ; GFX908-NEXT: {{  $}}
+    ; GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1
+    ; GFX908-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec, implicit-def $agpr1_agpr2
+    ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $agpr0_agpr1
+    ; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit $exec
+    ; GFX908-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr1, implicit $exec
+    ; GFX908-NEXT: S_ENDPGM 0, implicit $agpr1, implicit $agpr2, implicit $agpr3
+    ;
+    ; GFX90A-LABEL: name: a2_to_a2
+    ; GFX90A: liveins: $agpr0_agpr1
+    ; GFX90A-NEXT: {{  $}}
+    ; GFX90A-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit-def $agpr1_agpr2, implicit $agpr0_agpr1
+    ; GFX90A-NEXT: $agpr1 = V_ACCVGPR_MOV_B32 $agpr0, implicit $exec, implicit $agpr0_agpr1, implicit $exec
+    ; GFX90A-NEXT: $agpr3 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec
+    ; GFX90A-NEXT: S_ENDPGM 0, implicit $agpr1, implicit $agpr2, implicit $agpr3
+    ;
+    ; GFX940-LABEL: name: a2_to_a2
+    ; GFX940: liveins: $agpr0_agpr1
+    ; GFX940-NEXT: {{  $}}
+    ; GFX940-NEXT: $agpr2 = V_ACCVGPR_MOV_B32 $agpr1, implicit $exec, implicit-def $agpr1_agpr2, implicit $agpr0_agpr1
+    ; GFX940-NEXT: $agpr1 = V_ACCVGPR_MOV_B32 $agpr0, implicit $exec, implicit $agpr0_agpr1, implicit $exec
+    ; GFX940-NEXT: $agpr3 = V_ACCVGPR_MOV_B32 $agpr2, implicit $exec
+    ; GFX940-NEXT: S_ENDPGM 0, implicit $agpr1, implicit $agpr2, implicit $agpr3
+    $agpr1_agpr2 = COPY $agpr0_agpr1, implicit $exec
+    $agpr3 = COPY $agpr2
+    S_ENDPGM 0, implicit $agpr1, implicit $agpr2, implicit $agpr3
+...
+
 ---
 name:            a2_to_a2_kill
 tracksRegLiveness: true

diff --git a/llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir b/llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
@@ -12,7 +12,6 @@
   define amdgpu_gs void @mask_hazard_cndmask_dpp1() { ret void }
   define amdgpu_gs void @mask_hazard_cndmask_dpp2() { ret void }
   define amdgpu_gs void @mask_hazard_cndmask_dpp3() { ret void }
-  define amdgpu_gs void @mask_hazard_cndmask_dpp4() { ret void }
   define amdgpu_gs void @mask_hazard_addc1() { ret void }
   define amdgpu_gs void @mask_hazard_addc2() { ret void }
   define amdgpu_gs void @mask_hazard_addc3() { ret void }
@@ -156,16 +155,16 @@ body:            |
 ...
 
 ---
-name:            mask_hazard_cndmask_dpp4
+name:            mask_hazard_cndmask_dpp3
 body:            |
   bb.0:
-    ; GFX11-LABEL: name: mask_hazard_cndmask_dpp4
+    ; GFX11-LABEL: name: mask_hazard_cndmask_dpp3
     ; GFX11: $vgpr0 = V_CNDMASK_B16_e64_dpp $vgpr0, 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, 1, 15, 15, 1, implicit $exec
     ; GFX11-NEXT: $sgpr2_sgpr3 = S_CSELECT_B64 -1, 0, implicit $scc
     ; GFX11-NEXT: S_WAITCNT_DEPCTR 65534
     ; GFX11-NEXT: S_ENDPGM 0
     ;
-    ; GFX12-LABEL: name: mask_hazard_cndmask_dpp4
+    ; GFX12-LABEL: name: mask_hazard_cndmask_dpp3
     ; GFX12: $vgpr0 = V_CNDMASK_B16_e64_dpp $vgpr0, 0, $vgpr1, 0, $vgpr2, $sgpr2_sgpr3, 1, 15, 15, 1, implicit $exec
     ; GFX12-NEXT: $sgpr2_sgpr3 = S_CSELECT_B64 -1, 0, implicit $scc
     ; GFX12-NEXT: S_ENDPGM 0