Skip to content

Commit

Permalink
Remove some of the complexity-based canonicalization
Browse files Browse the repository at this point in the history
The idea behind is that the canonicalization allows us to handle
less pattern, because we know that some will be canonicalized away.
This is indeed very useful to e.g. know that constants are always
on the right.

However, the fact that arguments are also canonicalized to the
right seems like it may be doing more damage than good: This means
that writing tests to cover both commuted forms requires special
care ("thwart complexity-based canonicalization").

I think we should consider dropping this canonicalization to make
testing simpler.
  • Loading branch information
nikic committed Aug 16, 2024
1 parent 60bffe2 commit e7ea7d5
Show file tree
Hide file tree
Showing 268 changed files with 2,412 additions and 2,406 deletions.
25 changes: 11 additions & 14 deletions llvm/include/llvm/Transforms/InstCombine/InstCombiner.h
Original file line number Diff line number Diff line change
Expand Up @@ -132,21 +132,18 @@ class LLVM_LIBRARY_VISIBILITY InstCombiner {
/// This routine maps IR values to various complexity ranks:
/// 0 -> undef
/// 1 -> Constants
/// 2 -> Other non-instructions
/// 3 -> Arguments
/// 4 -> Cast and (f)neg/not instructions
/// 5 -> Other instructions
/// 2 -> Cast and (f)neg/not instructions
/// 3 -> Other instructions and arguments
static unsigned getComplexity(Value *V) {
if (isa<Instruction>(V)) {
if (isa<CastInst>(V) || match(V, m_Neg(PatternMatch::m_Value())) ||
match(V, m_Not(PatternMatch::m_Value())) ||
match(V, m_FNeg(PatternMatch::m_Value())))
return 4;
return 5;
}
if (isa<Argument>(V))
return 3;
return isa<Constant>(V) ? (isa<UndefValue>(V) ? 0 : 1) : 2;
if (isa<Constant>(V))
return isa<UndefValue>(V) ? 0 : 1;

if (isa<CastInst>(V) || match(V, m_Neg(PatternMatch::m_Value())) ||
match(V, m_Not(PatternMatch::m_Value())) ||
match(V, m_FNeg(PatternMatch::m_Value())))
return 2;

return 3;
}

/// Predicate canonicalization reduces the number of patterns that need to be
Expand Down
22 changes: 11 additions & 11 deletions llvm/test/Analysis/ValueTracking/known-power-of-two-urem.ll
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ define i64 @known_power_of_two_urem_phi(i64 %size, i1 %cmp, i1 %cmp1) {
; CHECK-NEXT: br label [[COND_END]]
; CHECK: cond.end:
; CHECK-NEXT: [[PHI1:%.*]] = phi i64 [ 4095, [[ENTRY:%.*]] ], [ [[PHI]], [[COND_TRUE_END]] ]
; CHECK-NEXT: [[UREM:%.*]] = and i64 [[PHI1]], [[SIZE:%.*]]
; CHECK-NEXT: [[UREM:%.*]] = and i64 [[SIZE:%.*]], [[PHI1]]
; CHECK-NEXT: ret i64 [[UREM]]
;
entry:
Expand Down Expand Up @@ -57,7 +57,7 @@ define i64 @known_power_of_two_urem_nested_expr(i64 %size, i1 %cmp, i1 %cmp1, i6
; CHECK: cond.end:
; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ [[SELECT]], [[COND_FALSE]] ], [ [[TMP1]], [[COND_TRUE]] ], [ [[PHI]], [[COND_END]] ]
; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[PHI]], -1
; CHECK-NEXT: [[UREM:%.*]] = and i64 [[TMP2]], [[SIZE:%.*]]
; CHECK-NEXT: [[UREM:%.*]] = and i64 [[SIZE:%.*]], [[TMP2]]
; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[UREM]], 10
; CHECK-NEXT: br i1 [[CMP2]], label [[COND_END]], label [[END:%.*]]
; CHECK: end:
Expand Down Expand Up @@ -119,7 +119,7 @@ define i64 @known_power_of_two_urem_loop_mul(i64 %size, i64 %a) {
; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ [[START]], [[ENTRY:%.*]] ], [ [[I:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[SUM:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[ADD:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[PHI]], -1
; CHECK-NEXT: [[UREM:%.*]] = and i64 [[TMP0]], [[SIZE:%.*]]
; CHECK-NEXT: [[UREM:%.*]] = and i64 [[SIZE:%.*]], [[TMP0]]
; CHECK-NEXT: [[ADD]] = add nuw i64 [[SUM]], [[UREM]]
; CHECK-NEXT: [[I]] = shl nuw i64 [[PHI]], 2
; CHECK-NEXT: [[ICMP:%.*]] = icmp ult i64 [[PHI]], 25000000
Expand Down Expand Up @@ -190,7 +190,7 @@ define i64 @known_power_of_two_urem_loop_shl(i64 %size, i64 %a) {
; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ [[START]], [[ENTRY:%.*]] ], [ [[I:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[SUM:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[ADD:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[PHI]], -1
; CHECK-NEXT: [[UREM:%.*]] = and i64 [[TMP0]], [[SIZE:%.*]]
; CHECK-NEXT: [[UREM:%.*]] = and i64 [[SIZE:%.*]], [[TMP0]]
; CHECK-NEXT: [[ADD]] = add nuw i64 [[SUM]], [[UREM]]
; CHECK-NEXT: [[I]] = shl nuw i64 [[PHI]], 1
; CHECK-NEXT: [[ICMP:%.*]] = icmp ult i64 [[PHI]], 50000000
Expand Down Expand Up @@ -225,7 +225,7 @@ define i64 @known_power_of_two_urem_loop_lshr(i64 %size, i64 %a) {
; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ [[START]], [[ENTRY:%.*]] ], [ [[I:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[SUM:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[ADD:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[PHI]], -1
; CHECK-NEXT: [[UREM:%.*]] = and i64 [[TMP0]], [[SIZE:%.*]]
; CHECK-NEXT: [[UREM:%.*]] = and i64 [[SIZE:%.*]], [[TMP0]]
; CHECK-NEXT: [[ADD]] = add nuw i64 [[SUM]], [[UREM]]
; CHECK-NEXT: [[I]] = lshr i64 [[PHI]], 1
; CHECK-NEXT: [[ICMP_NOT:%.*]] = icmp ult i64 [[PHI]], 2
Expand Down Expand Up @@ -260,7 +260,7 @@ define i64 @known_power_of_two_urem_loop_ashr(i64 %size, i64 %a) {
; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ 4096, [[ENTRY:%.*]] ], [ [[I:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[SUM:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[ADD:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = add nsw i64 [[PHI]], -1
; CHECK-NEXT: [[UREM:%.*]] = and i64 [[TMP0]], [[SIZE:%.*]]
; CHECK-NEXT: [[UREM:%.*]] = and i64 [[SIZE:%.*]], [[TMP0]]
; CHECK-NEXT: [[ADD]] = add nsw i64 [[SUM]], [[UREM]]
; CHECK-NEXT: [[I]] = lshr i64 [[PHI]], [[A:%.*]]
; CHECK-NEXT: [[ICMP_NOT:%.*]] = icmp eq i64 [[I]], 0
Expand Down Expand Up @@ -396,7 +396,7 @@ define i8 @known_power_of_two_rust_next_power_of_two(i8 %x, i8 %y) {
; CHECK-NEXT: [[TMP3:%.*]] = lshr i8 -1, [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt i8 [[X]], 1
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i8 [[TMP3]], i8 0
; CHECK-NEXT: [[R:%.*]] = and i8 [[TMP5]], [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = and i8 [[Y:%.*]], [[TMP5]]
; CHECK-NEXT: ret i8 [[R]]
;
%2 = add i8 %x, -1
Expand All @@ -414,7 +414,7 @@ define i8 @known_power_of_two_rust_next_power_of_two(i8 %x, i8 %y) {
define i8 @known_power_of_two_lshr_add_one_allow_zero(i8 %x, i8 %y) {
; CHECK-LABEL: @known_power_of_two_lshr_add_one_allow_zero(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 -1, [[X:%.*]]
; CHECK-NEXT: [[R:%.*]] = and i8 [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = and i8 [[Y:%.*]], [[TMP1]]
; CHECK-NEXT: ret i8 [[R]]
;
%4 = lshr i8 -1, %x
Expand All @@ -429,7 +429,7 @@ define i1 @known_power_of_two_lshr_add_one_nuw_deny_zero(i8 %x, i8 %y) {
; CHECK-LABEL: @known_power_of_two_lshr_add_one_nuw_deny_zero(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 -1, [[X:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = sub i8 -2, [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = or i8 [[TMP2]], [[Y:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = or i8 [[Y:%.*]], [[TMP2]]
; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[TMP3]], -1
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -446,7 +446,7 @@ define i1 @negative_known_power_of_two_lshr_add_one_deny_zero(i8 %x, i8 %y) {
; CHECK-LABEL: @negative_known_power_of_two_lshr_add_one_deny_zero(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 -1, [[X:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = sub i8 -2, [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = or i8 [[TMP2]], [[Y:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = or i8 [[Y:%.*]], [[TMP2]]
; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[TMP3]], -1
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -463,7 +463,7 @@ define i1 @negative_known_power_of_two_lshr_add_one_nsw_deny_zero(i8 %x, i8 %y)
; CHECK-LABEL: @negative_known_power_of_two_lshr_add_one_nsw_deny_zero(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 -1, [[X:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = sub i8 -2, [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = or i8 [[TMP2]], [[Y:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = or i8 [[Y:%.*]], [[TMP2]]
; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[TMP3]], -1
; CHECK-NEXT: ret i1 [[R]]
;
Expand Down
60 changes: 30 additions & 30 deletions llvm/test/Analysis/ValueTracking/known-power-of-two.ll
Original file line number Diff line number Diff line change
Expand Up @@ -16,8 +16,8 @@ declare i16 @llvm.umax.i16(i16, i16)
define i32 @pr25900(i32 %d) {
; CHECK-LABEL: define i32 @pr25900
; CHECK-SAME: (i32 [[D:%.*]]) {
; CHECK-NEXT: [[AND:%.*]] = ashr i32 [[D]], 31
; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 4, [[AND]]
; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[D]], 31
; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 4, [[ASHR]]
; CHECK-NEXT: ret i32 [[DIV]]
;
%and = and i32 %d, -2147483648
Expand All @@ -37,7 +37,7 @@ define i8 @trunc_is_pow2_or_zero(i16 %x, i8 %y) {
; CHECK-NEXT: [[XP2:%.*]] = shl i16 4, [[X]]
; CHECK-NEXT: [[XX:%.*]] = trunc i16 [[XP2]] to i8
; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[XX]], -1
; CHECK-NEXT: [[R:%.*]] = and i8 [[TMP1]], [[Y]]
; CHECK-NEXT: [[R:%.*]] = and i8 [[Y]], [[TMP1]]
; CHECK-NEXT: ret i8 [[R]]
;
%xp2 = shl i16 4, %x
Expand Down Expand Up @@ -67,7 +67,7 @@ define i1 @trunc_is_pow2_fail(i16 %x, i8 %y) {
; CHECK-SAME: (i16 [[X:%.*]], i8 [[Y:%.*]]) {
; CHECK-NEXT: [[XP2:%.*]] = shl i16 4, [[X]]
; CHECK-NEXT: [[XX:%.*]] = trunc i16 [[XP2]] to i8
; CHECK-NEXT: [[AND:%.*]] = and i8 [[XX]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i8 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AND]], [[XX]]
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -85,7 +85,7 @@ define i16 @bswap_is_pow2_or_zero(i16 %x, i16 %y) {
; CHECK-NEXT: [[XP2:%.*]] = shl i16 4, [[X]]
; CHECK-NEXT: [[XX:%.*]] = call i16 @llvm.bswap.i16(i16 [[XP2]])
; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[XX]], -1
; CHECK-NEXT: [[R:%.*]] = and i16 [[TMP1]], [[Y]]
; CHECK-NEXT: [[R:%.*]] = and i16 [[Y]], [[TMP1]]
; CHECK-NEXT: ret i16 [[R]]
;
%xp2 = shl i16 4, %x
Expand Down Expand Up @@ -115,7 +115,7 @@ define i1 @bswap_is_pow2(i16 %x, i16 %y) {
; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]]) {
; CHECK-NEXT: [[XP2:%.*]] = shl nuw i16 1, [[X]]
; CHECK-NEXT: [[XX:%.*]] = call i16 @llvm.bswap.i16(i16 [[XP2]])
; CHECK-NEXT: [[AND:%.*]] = and i16 [[XX]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp ne i16 [[AND]], 0
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -132,7 +132,7 @@ define i1 @bswap_is_pow2_fail(i16 %x, i16 %y) {
; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]]) {
; CHECK-NEXT: [[XP2:%.*]] = shl i16 2, [[X]]
; CHECK-NEXT: [[XX:%.*]] = call i16 @llvm.bswap.i16(i16 [[XP2]])
; CHECK-NEXT: [[AND:%.*]] = and i16 [[XX]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], [[XX]]
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -150,7 +150,7 @@ define i16 @bitreverse_is_pow2_or_zero(i16 %x, i16 %y) {
; CHECK-NEXT: [[XP2:%.*]] = shl i16 4, [[X]]
; CHECK-NEXT: [[XX:%.*]] = call i16 @llvm.bitreverse.i16(i16 [[XP2]])
; CHECK-NEXT: [[TMP1:%.*]] = add nsw i16 [[XX]], -1
; CHECK-NEXT: [[R:%.*]] = and i16 [[TMP1]], [[Y]]
; CHECK-NEXT: [[R:%.*]] = and i16 [[Y]], [[TMP1]]
; CHECK-NEXT: ret i16 [[R]]
;
%xp2 = shl i16 4, %x
Expand Down Expand Up @@ -180,7 +180,7 @@ define i1 @bitreverse_is_pow2(i16 %x, i16 %y) {
; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]]) {
; CHECK-NEXT: [[XP2:%.*]] = shl nuw i16 1, [[X]]
; CHECK-NEXT: [[XX:%.*]] = call i16 @llvm.bitreverse.i16(i16 [[XP2]])
; CHECK-NEXT: [[AND:%.*]] = and i16 [[XX]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp ne i16 [[AND]], 0
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -197,7 +197,7 @@ define i1 @bitreverse_is_pow2_fail(i16 %x, i16 %y) {
; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]]) {
; CHECK-NEXT: [[XP2:%.*]] = shl i16 2, [[X]]
; CHECK-NEXT: [[XX:%.*]] = call i16 @llvm.bitreverse.i16(i16 [[XP2]])
; CHECK-NEXT: [[AND:%.*]] = and i16 [[XX]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], [[XX]]
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -215,7 +215,7 @@ define i16 @fshl_is_pow2_or_zero(i16 %x, i16 %y, i16 %z) {
; CHECK-NEXT: [[XP2:%.*]] = shl i16 4, [[X]]
; CHECK-NEXT: [[XX:%.*]] = call i16 @llvm.fshl.i16(i16 [[XP2]], i16 [[XP2]], i16 [[Z]])
; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[XX]], -1
; CHECK-NEXT: [[R:%.*]] = and i16 [[TMP1]], [[Y]]
; CHECK-NEXT: [[R:%.*]] = and i16 [[Y]], [[TMP1]]
; CHECK-NEXT: ret i16 [[R]]
;
%xp2 = shl i16 4, %x
Expand Down Expand Up @@ -262,7 +262,7 @@ define i1 @fshl_is_pow2(i16 %x, i16 %y, i16 %z) {
; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]], i16 [[Z:%.*]]) {
; CHECK-NEXT: [[XP2:%.*]] = shl nuw i16 1, [[X]]
; CHECK-NEXT: [[XX:%.*]] = call i16 @llvm.fshl.i16(i16 [[XP2]], i16 [[XP2]], i16 [[Z]])
; CHECK-NEXT: [[AND:%.*]] = and i16 [[XX]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp ne i16 [[AND]], 0
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -279,7 +279,7 @@ define i1 @fshl_is_pow2_fail(i16 %x, i16 %y, i16 %z) {
; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]], i16 [[Z:%.*]]) {
; CHECK-NEXT: [[XP2:%.*]] = shl i16 2, [[X]]
; CHECK-NEXT: [[XX:%.*]] = call i16 @llvm.fshl.i16(i16 [[XP2]], i16 [[XP2]], i16 [[Z]])
; CHECK-NEXT: [[AND:%.*]] = and i16 [[XX]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], [[XX]]
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -297,7 +297,7 @@ define i16 @fshr_is_pow2_or_zero(i16 %x, i16 %y, i16 %z) {
; CHECK-NEXT: [[XP2:%.*]] = shl i16 4, [[X]]
; CHECK-NEXT: [[XX:%.*]] = call i16 @llvm.fshr.i16(i16 [[XP2]], i16 [[XP2]], i16 [[Z]])
; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[XX]], -1
; CHECK-NEXT: [[R:%.*]] = and i16 [[TMP1]], [[Y]]
; CHECK-NEXT: [[R:%.*]] = and i16 [[Y]], [[TMP1]]
; CHECK-NEXT: ret i16 [[R]]
;
%xp2 = shl i16 4, %x
Expand Down Expand Up @@ -344,7 +344,7 @@ define i1 @fshr_is_pow2(i16 %x, i16 %y, i16 %z) {
; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]], i16 [[Z:%.*]]) {
; CHECK-NEXT: [[XP2:%.*]] = shl nuw i16 1, [[X]]
; CHECK-NEXT: [[XX:%.*]] = call i16 @llvm.fshr.i16(i16 [[XP2]], i16 [[XP2]], i16 [[Z]])
; CHECK-NEXT: [[AND:%.*]] = and i16 [[XX]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp ne i16 [[AND]], 0
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -361,7 +361,7 @@ define i1 @fshr_is_pow2_fail(i16 %x, i16 %y, i16 %z) {
; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]], i16 [[Z:%.*]]) {
; CHECK-NEXT: [[XP2:%.*]] = shl i16 2, [[X]]
; CHECK-NEXT: [[XX:%.*]] = call i16 @llvm.fshr.i16(i16 [[XP2]], i16 [[XP2]], i16 [[Z]])
; CHECK-NEXT: [[AND:%.*]] = and i16 [[XX]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], [[XX]]
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -380,7 +380,7 @@ define i16 @mul_is_pow2_or_zero(i16 %x, i16 %y, i16 %z) {
; CHECK-NEXT: [[ZP2:%.*]] = shl i16 2, [[Z]]
; CHECK-NEXT: [[XX:%.*]] = mul i16 [[XP2]], [[ZP2]]
; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[XX]], -1
; CHECK-NEXT: [[R:%.*]] = and i16 [[TMP1]], [[Y]]
; CHECK-NEXT: [[R:%.*]] = and i16 [[Y]], [[TMP1]]
; CHECK-NEXT: ret i16 [[R]]
;
%xp2 = shl i16 4, %x
Expand Down Expand Up @@ -416,7 +416,7 @@ define i1 @mul_is_pow2(i16 %x, i16 %y, i16 %z) {
; CHECK-NEXT: [[ZP2:%.*]] = shl nuw nsw i16 2, [[ZSMALL]]
; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i16 [[XSMALL]], 2
; CHECK-NEXT: [[XX:%.*]] = shl nuw nsw i16 [[ZP2]], [[TMP1]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[XX]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp ne i16 [[AND]], 0
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -439,7 +439,7 @@ define i1 @mul_is_pow2_fail(i16 %x, i16 %y, i16 %z) {
; CHECK-NEXT: [[ZP2:%.*]] = shl nuw nsw i16 2, [[ZSMALL]]
; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i16 [[XSMALL]], 2
; CHECK-NEXT: [[XX:%.*]] = shl i16 [[ZP2]], [[TMP1]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[XX]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], [[XX]]
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -462,7 +462,7 @@ define i1 @mul_is_pow2_fail2(i16 %x, i16 %y, i16 %z) {
; CHECK-NEXT: [[XP2:%.*]] = shl nuw nsw i16 3, [[XSMALL]]
; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i16 [[ZSMALL]], 1
; CHECK-NEXT: [[XX:%.*]] = shl nuw nsw i16 [[XP2]], [[TMP1]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[XX]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], [[XX]]
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -482,7 +482,7 @@ define i1 @shl_is_pow2(i16 %x, i16 %y) {
; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]]) {
; CHECK-NEXT: [[XSMALL:%.*]] = and i16 [[X]], 7
; CHECK-NEXT: [[XX:%.*]] = shl nuw nsw i16 4, [[XSMALL]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[XX]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp ne i16 [[AND]], 0
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -499,7 +499,7 @@ define i1 @shl_is_pow2_fail(i16 %x, i16 %y) {
; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]]) {
; CHECK-NEXT: [[XSMALL:%.*]] = and i16 [[X]], 7
; CHECK-NEXT: [[XX:%.*]] = shl i16 512, [[XSMALL]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[XX]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], [[XX]]
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -516,7 +516,7 @@ define i1 @shl_is_pow2_fail2(i16 %x, i16 %y) {
; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]]) {
; CHECK-NEXT: [[XSMALL:%.*]] = and i16 [[X]], 7
; CHECK-NEXT: [[XX:%.*]] = shl nuw nsw i16 5, [[XSMALL]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[XX]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], [[XX]]
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -533,7 +533,7 @@ define i1 @lshr_is_pow2(i16 %x, i16 %y) {
; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]]) {
; CHECK-NEXT: [[XSMALL:%.*]] = and i16 [[X]], 7
; CHECK-NEXT: [[XX:%.*]] = lshr exact i16 512, [[XSMALL]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[XX]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp ne i16 [[AND]], 0
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -550,7 +550,7 @@ define i1 @lshr_is_pow2_fail(i16 %x, i16 %y) {
; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]]) {
; CHECK-NEXT: [[XSMALL:%.*]] = and i16 [[X]], 7
; CHECK-NEXT: [[XX:%.*]] = lshr i16 4, [[XSMALL]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[XX]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], [[XX]]
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -567,7 +567,7 @@ define i1 @lshr_is_pow2_fail2(i16 %x, i16 %y) {
; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]]) {
; CHECK-NEXT: [[XSMALL:%.*]] = and i16 [[X]], 7
; CHECK-NEXT: [[XX:%.*]] = lshr i16 513, [[XSMALL]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[XX]], [[Y]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], [[XX]]
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -584,7 +584,7 @@ define i1 @and_is_pow2(i16 %x, i16 %y) {
; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]]) {
; CHECK-NEXT: [[XNZ:%.*]] = or i16 [[X]], 4
; CHECK-NEXT: [[X_NEG:%.*]] = sub nsw i16 0, [[XNZ]]
; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[X_NEG]], [[Y]]
; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[Y]], [[X_NEG]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[TMP1]], [[XNZ]]
; CHECK-NEXT: [[R:%.*]] = icmp ne i16 [[AND]], 0
; CHECK-NEXT: ret i1 [[R]]
Expand All @@ -602,8 +602,8 @@ define i1 @and_is_pow2_fail(i16 %x, i16 %y) {
; CHECK-LABEL: define i1 @and_is_pow2_fail
; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]]) {
; CHECK-NEXT: [[X_NEG:%.*]] = sub i16 0, [[X]]
; CHECK-NEXT: [[XX:%.*]] = and i16 [[X_NEG]], [[X]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[XX]], [[Y]]
; CHECK-NEXT: [[XX:%.*]] = and i16 [[X]], [[X_NEG]]
; CHECK-NEXT: [[AND:%.*]] = and i16 [[Y]], [[XX]]
; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[AND]], [[XX]]
; CHECK-NEXT: ret i1 [[R]]
;
Expand All @@ -619,7 +619,7 @@ define i16 @i1_is_pow2_or_zero(i1 %x, i16 %y) {
; CHECK-LABEL: define i16 @i1_is_pow2_or_zero
; CHECK-SAME: (i1 [[X:%.*]], i16 [[Y:%.*]]) {
; CHECK-NEXT: [[XX:%.*]] = zext i1 [[X]] to i16
; CHECK-NEXT: [[R:%.*]] = or i16 [[XX]], [[Y]]
; CHECK-NEXT: [[R:%.*]] = or i16 [[Y]], [[XX]]
; CHECK-NEXT: ret i16 [[R]]
;
%xx = zext i1 %x to i16
Expand Down
Loading

0 comments on commit e7ea7d5

Please sign in to comment.