Inaccuracies in the znver1 scheduling model: vpmov*, vtestp*, vps*v*, vcmp*

[ritter-x2a]

We encountered several more inaccuracies in the znver1 scheduling model:

• The vpmov(s|z)x(b|w|q) instructions that write to ymm registers are predicted faster by llvm-mca than they run, e.g. (numbers are inverse throughput):

# LLVM-EXEGESIS-DEFREG YMM10 42
# LLVM-EXEGESIS-DEFREG YMM7 42
.intel_syntax noprefix
vpmovsxbw ymm10, xmm7  # llvm-mca: 0.5cy, llvm-exegesis: 2.0cy (3 uops)

It seems like they use the information for the xmm version, which is faster according to uops.info.
AMD's table doesn't include these versions of the instructions.

• Similarly, the vtestp(s|d) instructions with ymm operands are predicted faster by llvm-mca than they run, e.g.:

# LLVM-EXEGESIS-DEFREG YMM10 42
# LLVM-EXEGESIS-DEFREG YMM7 43
.intel_syntax noprefix
vtestps ymm10, ymm7  # llvm-mca: 0.28cy, llvm-exegesis: 2.0cy (3 uops)

For the xmm version, llvm-mca predicts the same whereas llvm-exegesis measures an inverse throughput of 1.0.
The AMD table claims a throughput of 2, i.e. an inverse throughput of 0.5, which agrees with neither of those.
uops.info agrees with the llvm-exegesis measurements.

• The AVX2 variable shifts vps(llvd|llvq|ravd|ravq|rlvd|rlvq) with 3 register operands or 2 register operands and a memory operand are predicted too fast by llvm-mca, e.g.:

# LLVM-EXEGESIS-DEFREG XMM13 43
# LLVM-EXEGESIS-DEFREG XMM15 42
# LLVM-EXEGESIS-LIVEIN RDI
.intel_syntax noprefix
vpsllvd xmm13, xmm15, xmmword ptr [rdi+42]  # llvm-mca: 0.6cy, llvm-exegesis: 2.0cy (1*ZnFPU1)

and

# LLVM-EXEGESIS-DEFREG YMM13 43
# LLVM-EXEGESIS-DEFREG YMM15 42
# LLVM-EXEGESIS-DEFREG YMM7 8
.intel_syntax noprefix
vpsllvd ymm13, ymm15, ymm7  # llvm-mca: 0.5, llvm-exegesis: 4.0 (2*ZnFPU1)

The AMD table does not mention those instructions, the uops.info measurements agree with llvm-exegesis on the throughput, but not the port usage.

• SSE and AVX CMP instructions (V)CMPcc(SS|PS|PD|SD) have wrong (inverse) throughput / resource usage and latency:
  For throughput e.g.:

# LLVM-EXEGESIS-DEFREG XMM1 43
# LLVM-EXEGESIS-DEFREG XMM2 42
# LLVM-EXEGESIS-DEFREG XMM3 42
.intel_syntax noprefix
vcmpss xmm3, xmm1, xmm2, 1  # llvm-mca: 1.0cy, llvm-exegesis: 0.5cy

and for latency:

# LLVM-EXEGESIS-DEFREG XMM1 43
# LLVM-EXEGESIS-DEFREG XMM2 42
.intel_syntax noprefix
vcmpss xmm1, xmm1, xmm2, 1  # llvm-mca: 3.0cy, llvm-exegesis: 1.0cy

AMD's table reports them, consistently with llvm-exegesis, as having a latency of 1 and a throughput of 2, since they use only one FPU0/1 uop (that is for the xmm version, for the ymm version the throughput is 1 with two such uops).

Sorry for the long issue; sadly, there seems to be a lot to find.
Please do tell me if I should separate these into multiple issues!

[llvmbot]

@llvm/issue-subscribers-backend-x86

[RKSimon]

@Fabian-R Something you could try is running llvm-exegesis for all supported instruction with just 1 run for each mode :

https://llvm.org/docs/CommandGuide/llvm-exegesis.html

llvm-exegesis -mode={latency,inverse_throughput,uops} -opcode-index=-1 > benchmarks.yaml

You can then create a html dump of all discrepancies with the model:

llvm-exegesis -mode=analysis -benchmarks-file=benchmarks.yaml -analysis-clusters-output-file=clusters.csv -analysis-inconsistencies-output-file=inconsistencies.html

And then post the yaml / inconsistencies files here

[ritter-x2a]

The first command eventually terminates with a segfault, but it still produces 500k lines of output. I had to remove "Check generated assembly with: ..." lines from this to successfully run the second command. The results are in the attached tar.gz archive:
exegesis_results_zenplus.tar.gz

[RKSimon]

Resolving as I think we've covered all the reported mismatches now