[LV] Reuse VPReplicateRecipe to handle scalar stores in exit block. #106342

Mel-Chen · 2024-08-28T07:17:15Z

This patch separates the computation of the final reduction result and the intermediate stores of reduction.

llvmbot · 2024-08-28T07:17:49Z

@llvm/pr-subscribers-llvm-transforms

Author: Mel Chen (Mel-Chen)

Changes

This patch separates the computation of the final reduction result and the intermediate stores of reduction.

Full diff: https://github.com/llvm/llvm-project/pull/106342.diff

4 Files Affected:

(modified) llvm/lib/Transforms/Vectorize/LoopVectorize.cpp (+32-50)
(modified) llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp (-8)
(modified) llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll (+16-16)
(modified) llvm/test/Transforms/LoopVectorize/vplan-printing.ll (+1)

diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 6850b502939f58..f855d5f2f8de25 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -2388,8 +2388,8 @@ void InnerLoopVectorizer::scalarizeInstruction(const Instruction *Instr,
     AC->registerAssumption(II);
 
   // End if-block.
-  bool IfPredicateInstr = RepRecipe->getParent()->getParent()->isReplicator();
-  if (IfPredicateInstr)
+  const VPRegionBlock *Region = RepRecipe->getParent()->getParent();
+  if (Region && Region->isReplicator())
     PredicatedInstructions.push_back(Cloned);
 }
 
@@ -8901,6 +8901,9 @@ LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes(VFRange &Range) {
         bool NeedsBlends = BB != HeaderBB && !BB->phis().empty();
         return Legal->blockNeedsPredication(BB) || NeedsBlends;
       });
+  auto *MiddleVPBB =
+      cast<VPBasicBlock>(Plan->getVectorLoopRegion()->getSingleSuccessor());
+  VPBasicBlock::iterator MBIP = MiddleVPBB->getFirstNonPhi();
   for (BasicBlock *BB : make_range(DFS.beginRPO(), DFS.endRPO())) {
     // Relevant instructions from basic block BB will be grouped into VPRecipe
     // ingredients and fill a new VPBasicBlock.
@@ -8931,8 +8934,17 @@ LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes(VFRange &Range) {
       // with the final reduction value will be added to the exit block
       StoreInst *SI;
       if ((SI = dyn_cast<StoreInst>(&I)) &&
-          Legal->isInvariantAddressOfReduction(SI->getPointerOperand()))
+          Legal->isInvariantAddressOfReduction(SI->getPointerOperand())) {
+        // Only create recipe for the last intermediate store of the reduction.
+        if (!Legal->isInvariantStoreOfReduction(SI))
+          continue;
+        auto *Recipe = new VPReplicateRecipe(
+            SI, RecipeBuilder.mapToVPValues(Instr->operands()),
+            true /* IsUniform */);
+        RecipeBuilder.setRecipe(SI, Recipe);
+        Recipe->insertBefore(*MiddleVPBB, MBIP);
         continue;
+      }
 
       VPRecipeBase *Recipe =
           RecipeBuilder.tryToCreateWidenRecipe(Instr, Operands, Range, VPBB);
@@ -9130,51 +9142,13 @@ void LoopVectorizationPlanner::adjustRecipesForReductions(
   using namespace VPlanPatternMatch;
   VPRegionBlock *VectorLoopRegion = Plan->getVectorLoopRegion();
   VPBasicBlock *Header = VectorLoopRegion->getEntryBasicBlock();
-  // Gather all VPReductionPHIRecipe and sort them so that Intermediate stores
-  // sank outside of the loop would keep the same order as they had in the
-  // original loop.
-  SmallVector<VPReductionPHIRecipe *> ReductionPHIList;
-  for (VPRecipeBase &R : Header->phis()) {
-    if (auto *ReductionPhi = dyn_cast<VPReductionPHIRecipe>(&R))
-      ReductionPHIList.emplace_back(ReductionPhi);
-  }
-  bool HasIntermediateStore = false;
-  stable_sort(ReductionPHIList,
-              [this, &HasIntermediateStore](const VPReductionPHIRecipe *R1,
-                                            const VPReductionPHIRecipe *R2) {
-                auto *IS1 = R1->getRecurrenceDescriptor().IntermediateStore;
-                auto *IS2 = R2->getRecurrenceDescriptor().IntermediateStore;
-                HasIntermediateStore |= IS1 || IS2;
-
-                // If neither of the recipes has an intermediate store, keep the
-                // order the same.
-                if (!IS1 && !IS2)
-                  return false;
-
-                // If only one of the recipes has an intermediate store, then
-                // move it towards the beginning of the list.
-                if (IS1 && !IS2)
-                  return true;
-
-                if (!IS1 && IS2)
-                  return false;
-
-                // If both recipes have an intermediate store, then the recipe
-                // with the later store should be processed earlier. So it
-                // should go to the beginning of the list.
-                return DT->dominates(IS2, IS1);
-              });
-
-  if (HasIntermediateStore && ReductionPHIList.size() > 1)
-    for (VPRecipeBase *R : ReductionPHIList)
-      R->moveBefore(*Header, Header->getFirstNonPhi());
-
   for (VPRecipeBase &R : Header->phis()) {
     auto *PhiR = dyn_cast<VPReductionPHIRecipe>(&R);
     if (!PhiR || !PhiR->isInLoop() || (MinVF.isScalar() && !PhiR->isOrdered()))
       continue;
 
     const RecurrenceDescriptor &RdxDesc = PhiR->getRecurrenceDescriptor();
+    StoreInst* IntermediateStore = RdxDesc.IntermediateStore;
     RecurKind Kind = RdxDesc.getRecurrenceKind();
     assert(!RecurrenceDescriptor::isAnyOfRecurrenceKind(Kind) &&
            "AnyOf reductions are not allowed for in-loop reductions");
@@ -9187,9 +9161,13 @@ void LoopVectorizationPlanner::adjustRecipesForReductions(
       for (VPUser *U : Cur->users()) {
         auto *UserRecipe = cast<VPSingleDefRecipe>(U);
         if (!UserRecipe->getParent()->getEnclosingLoopRegion()) {
-          assert(match(U, m_Binary<VPInstruction::ExtractFromEnd>(
-                              m_VPValue(), m_VPValue())) &&
-                 "U must be an ExtractFromEnd VPInstruction");
+          assert((match(U, m_Binary<VPInstruction::ExtractFromEnd>(
+                               m_VPValue(), m_VPValue())) ||
+                  (isa<VPReplicateRecipe>(U) &&
+                   cast<VPReplicateRecipe>(U)->getUnderlyingValue() ==
+                       IntermediateStore)) &&
+                 "U must be either an ExtractFromEnd VPInstruction or a "
+                 "uniform store sourced from the intermediate store.");
           continue;
         }
         Worklist.insert(UserRecipe);
@@ -9304,6 +9282,7 @@ void LoopVectorizationPlanner::adjustRecipesForReductions(
       continue;
 
     const RecurrenceDescriptor &RdxDesc = PhiR->getRecurrenceDescriptor();
+    StoreInst *IntermediateStore = RdxDesc.IntermediateStore;
     // Adjust AnyOf reductions; replace the reduction phi for the selected value
     // with a boolean reduction phi node to check if the condition is true in
     // any iteration. The final value is selected by the final
@@ -9406,11 +9385,14 @@ void LoopVectorizationPlanner::adjustRecipesForReductions(
     auto *FinalReductionResult = new VPInstruction(
         VPInstruction::ComputeReductionResult, {PhiR, NewExitingVPV}, ExitDL);
     FinalReductionResult->insertBefore(*MiddleVPBB, IP);
-    OrigExitingVPV->replaceUsesWithIf(FinalReductionResult, [](VPUser &User,
-                                                               unsigned) {
-      return match(&User, m_Binary<VPInstruction::ExtractFromEnd>(m_VPValue(),
-                                                                  m_VPValue()));
-    });
+    OrigExitingVPV->replaceUsesWithIf(
+        FinalReductionResult, [IntermediateStore](VPUser &User, unsigned) {
+          return match(&User, m_Binary<VPInstruction::ExtractFromEnd>(
+                                  m_VPValue(), m_VPValue())) ||
+                 (isa<VPReplicateRecipe>(&User) &&
+                  cast<VPReplicateRecipe>(&User)->getUnderlyingValue() ==
+                      IntermediateStore);
+        });
   }
 
   VPlanTransforms::clearReductionWrapFlags(*Plan);
diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
index 53b28a692059f6..2689f9cf31117c 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
@@ -601,14 +601,6 @@ Value *VPInstruction::generatePerPart(VPTransformState &State, unsigned Part) {
                              : Builder.CreateZExt(ReducedPartRdx, PhiTy);
     }
 
-    // If there were stores of the reduction value to a uniform memory address
-    // inside the loop, create the final store here.
-    if (StoreInst *SI = RdxDesc.IntermediateStore) {
-      auto *NewSI = Builder.CreateAlignedStore(
-          ReducedPartRdx, SI->getPointerOperand(), SI->getAlign());
-      propagateMetadata(NewSI, SI);
-    }
-
     return ReducedPartRdx;
   }
   case VPInstruction::ExtractFromEnd: {
diff --git a/llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll b/llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
index 8cf4e77a0d4990..0d9918b74a2ff2 100644
--- a/llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
+++ b/llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
@@ -596,10 +596,10 @@ exit:                                             ; preds = %for.body
 define void @reduc_add_mul_store_same_ptr(ptr %dst, ptr readonly %src) {
 ; CHECK-LABEL: define void @reduc_add_mul_store_same_ptr
 ; CHECK:       middle.block:
-; CHECK-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[TMP3:%.*]])
-; CHECK-NEXT:    store i32 [[TMP4]], ptr %dst, align 4
-; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP1:%.*]])
-; CHECK-NEXT:    store i32 [[TMP2]], ptr %dst, align 4
+; CHECK-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP3:%.*]])
+; CHECK-NEXT:    [[TMP7:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[TMP4:%.*]])
+; CHECK-NEXT:    store i32 [[TMP6]], ptr %dst, align 4
+; CHECK-NEXT:    store i32 [[TMP7]], ptr %dst, align 4
 ;
 entry:
   br label %for.body
@@ -625,10 +625,10 @@ exit:
 define void @reduc_mul_add_store_same_ptr(ptr %dst, ptr readonly %src) {
 ; CHECK-LABEL: define void @reduc_mul_add_store_same_ptr
 ; CHECK:       middle.block:
-; CHECK-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP3:%.*]])
-; CHECK-NEXT:    store i32 [[TMP4]], ptr %dst, align 4
-; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[TMP1:%.*]])
-; CHECK-NEXT:    store i32 [[TMP2]], ptr %dst, align 4
+; CHECK-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP4:%.*]])
+; CHECK-NEXT:    [[TMP7:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[TMP3:%.*]])
+; CHECK-NEXT:    store i32 [[TMP7]], ptr %dst, align 4
+; CHECK-NEXT:    store i32 [[TMP6]], ptr %dst, align 4
 ;
 entry:
   br label %for.body
@@ -655,10 +655,10 @@ exit:
 define void @reduc_add_mul_store_different_ptr(ptr %dst1, ptr %dst2, ptr readonly %src) {
 ; CHECK-LABEL: define void @reduc_add_mul_store_different_ptr
 ; CHECK:       middle.block:
-; CHECK-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[TMP3:%.*]])
-; CHECK-NEXT:    store i32 [[TMP4]], ptr %dst2, align 4
-; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP1:%.*]])
-; CHECK-NEXT:    store i32 [[TMP2]], ptr %dst1, align 4
+; CHECK-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP3:%.*]])
+; CHECK-NEXT:    [[TMP7:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[TMP4:%.*]])
+; CHECK-NEXT:    store i32 [[TMP6]], ptr %dst1, align 4
+; CHECK-NEXT:    store i32 [[TMP7]], ptr %dst2, align 4
 ;
 entry:
   br label %for.body
@@ -684,10 +684,10 @@ exit:
 define void @reduc_mul_add_store_different_ptr(ptr %dst1, ptr %dst2, ptr readonly %src) {
 ; CHECK-LABEL: define void @reduc_mul_add_store_different_ptr
 ; CHECK:       middle.block:
-; CHECK-NEXT:    [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP3:%.*]])
-; CHECK-NEXT:    store i32 [[TMP4]], ptr %dst2, align 4
-; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[TMP1:%.*]])
-; CHECK-NEXT:    store i32 [[TMP2]], ptr %dst1, align 4
+; CHECK-NEXT:    [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP4:%.*]])
+; CHECK-NEXT:    [[TMP7:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[TMP3:%.*]])
+; CHECK-NEXT:    store i32 [[TMP7]], ptr %dst1, align 4
+; CHECK-NEXT:    store i32 [[TMP6]], ptr %dst2, align 4
 ;
 entry:
   br label %for.body
diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll
index f18ed825a6b886..af74b18211f208 100644
--- a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll
+++ b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll
@@ -212,6 +212,7 @@ define void @print_reduction_with_invariant_store(i64 %n, ptr noalias %y, ptr no
 ; CHECK-EMPTY:
 ; CHECK-NEXT: middle.block:
 ; CHECK-NEXT:   EMIT vp<[[RED_RES:.+]]> = compute-reduction-result ir<%red>, ir<%red.next>
+; CHECK-NEXT:   CLONE store vp<[[RED_RES]]>, ir<%dst>
 ; CHECK-NEXT:   EMIT vp<[[CMP:%.+]]> = icmp eq ir<%n>, vp<[[VEC_TC]]>
 ; CHECK-NEXT:   EMIT branch-on-cond vp<[[CMP]]>
 ; CHECK-NEXT: Successor(s): ir-bb<for.end>, scalar.ph

github-actions · 2024-08-28T07:20:49Z

✅ With the latest revision this PR passed the C/C++ code formatter.

Mel-Chen · 2024-09-02T06:39:03Z

ping

fhahn

Thanks this looks like a nice use of VPReplicateRecipe to simplify handing of reductions with a store to an invariant address.

Unless I am missing something, using VPReplicateRecipe here should be fine, but would be good do add some extra assertions to guard against unintentional mis-use

fhahn · 2024-08-28T08:29:20Z

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

  for (VPRecipeBase &R : Header->phis()) {
    auto *PhiR = dyn_cast<VPReductionPHIRecipe>(&R);
    if (!PhiR || !PhiR->isInLoop() || (MinVF.isScalar() && !PhiR->isOrdered()))
      continue;

    const RecurrenceDescriptor &RdxDesc = PhiR->getRecurrenceDescriptor();
+    StoreInst *IntermediateStore = RdxDesc.IntermediateStore;


only used in assertion, will need to by sunk into assert (preferable) or mark as potentially unused to avoid warning

Make sense, thanks.
912cccf

fhahn · 2024-08-28T08:29:28Z

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

@@ -9304,6 +9282,7 @@ void LoopVectorizationPlanner::adjustRecipesForReductions(
      continue;

    const RecurrenceDescriptor &RdxDesc = PhiR->getRecurrenceDescriptor();
+    StoreInst *IntermediateStore = RdxDesc.IntermediateStore;


only used in assertion, will need to by sunk into assert (preferable) or mark as potentially unused to avoid warning

It is not used in assertion. It used in OrigExitingVPV->replaceUsesWithIf.
Would you like to move it closer to where it will be used?

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Mel-Chen · 2024-09-10T06:57:22Z

Ping

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

fhahn · 2024-09-24T06:34:22Z

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

@@ -8956,8 +8965,17 @@ LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes(VFRange &Range) {
      // with the final reduction value will be added to the exit block


Update comment, possibly merge with the new one below?

76d4dde
And replace last with final for aligning the term with the comment of isInvariantStoreOfReduction.

/// Returns True if given store is a final invariant store of one of the /// reductions found in the loop. bool isInvariantStoreOfReduction(StoreInst *SI);

fhahn · 2024-09-24T06:35:46Z

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

+          assert((match(U, m_Binary<VPInstruction::ExtractFromEnd>(
+                               m_VPValue(), m_VPValue())) ||
+                  (isa<VPReplicateRecipe>(U) &&
+                   cast<VPReplicateRecipe>(U)->getUnderlyingValue() ==
+                       RdxDesc.IntermediateStore)) &&
+                 "U must be either an ExtractFromEnd VPInstruction or a "
+                 "uniform store sourced from the intermediate store.");


probably time to remove the assert or adjust to allow any recipe in the middle block instead of checking specific recipes?

Agree.
a3a6614

fhahn

LGTM, thanks, with one remaining suggestion

fhahn · 2024-09-26T10:21:43Z

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

+        auto *Recipe = new VPReplicateRecipe(
+            SI, RecipeBuilder.mapToVPValues(Instr->operands()),
+            true /* IsUniform */);
+        RecipeBuilder.setRecipe(SI, Recipe);


Is this needed?

Thank you for your suggestion :)
It has been removed. After confirm, I think it is not needed, as there is no use case for it at the moment.

Refine the update lambda of ComputeReductionResult. Co-authored-by: Florian Hahn <[email protected]>

…lvm#106342) This patch separates the computation of the final reduction result and the intermediate stores of reduction. --------- Co-authored-by: Florian Hahn <[email protected]>

Mel-Chen requested review from fhahn, npanchen, davemgreen, igogo-x86, huntergr-arm, ayalz and david-arm August 28, 2024 07:17

llvmbot added vectorizers llvm:transforms labels Aug 28, 2024

Mel-Chen mentioned this pull request Aug 28, 2024

[LV][VPlan] Introduce VPScalarStore recipe to handle scalar stores in exit block. #93148

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Mel-Chen force-pushed the rdx-replicate-store branch from 3ce39e4 to 8d8635f Compare August 28, 2024 07:31

fhahn reviewed Sep 3, 2024

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Mel-Chen force-pushed the rdx-replicate-store branch from 8d8635f to 40b40fa Compare September 4, 2024 09:40

Mel-Chen requested a review from fhahn September 9, 2024 05:52

Mel-Chen force-pushed the rdx-replicate-store branch from 40b40fa to 206be4f Compare September 10, 2024 06:57

fhahn reviewed Sep 11, 2024

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Mel-Chen force-pushed the rdx-replicate-store branch from 8df0b23 to c3b41e2 Compare September 23, 2024 14:00

Mel-Chen requested a review from fhahn September 23, 2024 14:02

fhahn reviewed Sep 24, 2024

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Mel-Chen force-pushed the rdx-replicate-store branch from c3b41e2 to a3a6614 Compare September 26, 2024 08:08

Mel-Chen requested a review from fhahn September 26, 2024 08:18

fhahn approved these changes Sep 26, 2024

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Mel-Chen added 4 commits September 29, 2024 22:43

Init implement

c5092a4

Move intermediate store into assertion section.

8f5f05a

Add assertion for scalarizeInstruction

55bccde

Check the address is defined outside vector region.

765fac8

Mel-Chen and others added 6 commits September 29, 2024 22:43

Update llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

5b8ea2a

Refine the update lambda of ComputeReductionResult. Co-authored-by: Florian Hahn <[email protected]>

Fix the suggestion code

b9a8898

Rebase and update

34e2615

Updated comments

7cd0ac1

Update assertion

591bcf2

Remove setRecipe

b494e9c

Mel-Chen force-pushed the rdx-replicate-store branch from a3a6614 to b494e9c Compare September 30, 2024 06:00

Mel-Chen merged commit f8373cb into llvm:main Sep 30, 2024
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[LV] Reuse VPReplicateRecipe to handle scalar stores in exit block. #106342

[LV] Reuse VPReplicateRecipe to handle scalar stores in exit block. #106342

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Mel-Chen Sep 30, 2024

		@@ -8956,8 +8965,17 @@ LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes(VFRange &Range) {
		// with the final reduction value will be added to the exit block

[LV] Reuse VPReplicateRecipe to handle scalar stores in exit block. #106342

[LV] Reuse VPReplicateRecipe to handle scalar stores in exit block. #106342

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