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[ARM][ISel] Fix crash of ISD::FMINNUM/FMAXNUM #65849

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[ARM][ISel] Fix crash of ISD::FMINNUM/FMAXNUM
The instruction of ISD::FMINNUM/FMAXNUM should be legal if HasFPARMv8 && HasNEON.
For the combination of armv7+fp-armv8, armv7 imply the feature HasNEON
on, and fp-armv8 matchs the feature HasFPARMv8, so it is legal.

Fixes #65820
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vfdff committed Sep 13, 2023
commit cfa778db0cb332d9ef72b9a09e18dc4cec03d800
16 changes: 8 additions & 8 deletions llvm/lib/Target/ARM/ARMInstrNEON.td
Original file line number Diff line number Diff line change
@@ -5711,19 +5711,19 @@ let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" i
def NEON_VMAXNMNDf : N3VDIntnp<0b00110, 0b00, 0b1111, 0, 1,
N3RegFrm, NoItinerary, "vmaxnm", "f32",
v2f32, v2f32, fmaxnum, 1>,
Requires<[HasV8, HasNEON]>;
Requires<[HasFPARMv8, HasNEON]>;
def NEON_VMAXNMNQf : N3VQIntnp<0b00110, 0b00, 0b1111, 1, 1,
N3RegFrm, NoItinerary, "vmaxnm", "f32",
v4f32, v4f32, fmaxnum, 1>,
Requires<[HasV8, HasNEON]>;
Requires<[HasFPARMv8, HasNEON]>;
def NEON_VMAXNMNDh : N3VDIntnp<0b00110, 0b01, 0b1111, 0, 1,
N3RegFrm, NoItinerary, "vmaxnm", "f16",
v4f16, v4f16, fmaxnum, 1>,
Requires<[HasV8, HasNEON, HasFullFP16]>;
Requires<[HasFPARMv8, HasNEON, HasFullFP16]>;
def NEON_VMAXNMNQh : N3VQIntnp<0b00110, 0b01, 0b1111, 1, 1,
N3RegFrm, NoItinerary, "vmaxnm", "f16",
v8f16, v8f16, fmaxnum, 1>,
Requires<[HasV8, HasNEON, HasFullFP16]>;
Requires<[HasFPARMv8, HasNEON, HasFullFP16]>;
}

// VMIN : Vector Minimum
@@ -5753,19 +5753,19 @@ let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" i
def NEON_VMINNMNDf : N3VDIntnp<0b00110, 0b10, 0b1111, 0, 1,
N3RegFrm, NoItinerary, "vminnm", "f32",
v2f32, v2f32, fminnum, 1>,
Requires<[HasV8, HasNEON]>;
Requires<[HasFPARMv8, HasNEON]>;
def NEON_VMINNMNQf : N3VQIntnp<0b00110, 0b10, 0b1111, 1, 1,
N3RegFrm, NoItinerary, "vminnm", "f32",
v4f32, v4f32, fminnum, 1>,
Requires<[HasV8, HasNEON]>;
Requires<[HasFPARMv8, HasNEON]>;
def NEON_VMINNMNDh : N3VDIntnp<0b00110, 0b11, 0b1111, 0, 1,
N3RegFrm, NoItinerary, "vminnm", "f16",
v4f16, v4f16, fminnum, 1>,
Requires<[HasV8, HasNEON, HasFullFP16]>;
Requires<[HasFPARMv8, HasNEON, HasFullFP16]>;
def NEON_VMINNMNQh : N3VQIntnp<0b00110, 0b11, 0b1111, 1, 1,
N3RegFrm, NoItinerary, "vminnm", "f16",
v8f16, v8f16, fminnum, 1>,
Requires<[HasV8, HasNEON, HasFullFP16]>;
Requires<[HasFPARMv8, HasNEON, HasFullFP16]>;
}

// Vector Pairwise Operations.
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