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[SPIR-V] Fix 64-bit integer literal printing #66686

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Sep 20, 2023
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[SPIR-V] Fix 64-bit integer literal printing #66686

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4 changes: 3 additions & 1 deletion llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
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Expand Up @@ -169,7 +169,9 @@ void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
}
case SPIRV::OpConstantI:
case SPIRV::OpConstantF:
printOpConstantVarOps(MI, NumFixedOps, OS);
// The last fixed operand along with any variadic operands that follow
// are part of the variable value.
printOpConstantVarOps(MI, NumFixedOps - 1, OS);
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break;
default:
printRemainingVariableOps(MI, NumFixedOps, OS);
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4 changes: 2 additions & 2 deletions llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
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Expand Up @@ -217,9 +217,9 @@ def ConstPseudoNull: IntImmLeaf<i64, [{ return Imm.isZero(); }]>;

multiclass IntFPImm<bits<16> opCode, string name> {
def I: Op<opCode, (outs ID:$dst), (ins TYPE:$type, ID:$src, variable_ops),
"$dst = "#name#" $type $src", [(set ID:$dst, (assigntype PseudoConstI:$src, TYPE:$type))]>;
"$dst = "#name#" $type", [(set ID:$dst, (assigntype PseudoConstI:$src, TYPE:$type))]>;
def F: Op<opCode, (outs ID:$dst), (ins TYPE:$type, fID:$src, variable_ops),
"$dst = "#name#" $type $src", [(set ID:$dst, (assigntype PseudoConstF:$src, TYPE:$type))]>;
"$dst = "#name#" $type", [(set ID:$dst, (assigntype PseudoConstF:$src, TYPE:$type))]>;
}

def OpConstantTrue: Op<41, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantTrue $src_ty",
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/SPIRV/atomicrmw.ll
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@@ -1,10 +1,10 @@
; RUN: llc -O0 -opaque-pointers=0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s

; CHECK: %[[#Int:]] = OpTypeInt 32 0
; CHECK-DAG: %[[#Scope_Device:]] = OpConstant %[[#Int]] 1 {{$}}
; CHECK-DAG: %[[#Scope_Device:]] = OpConstant %[[#Int]] 1{{$}}
; CHECK-DAG: %[[#MemSem_Relaxed:]] = OpConstant %[[#Int]] 0
; CHECK-DAG: %[[#MemSem_Acquire:]] = OpConstant %[[#Int]] 2
; CHECK-DAG: %[[#MemSem_Release:]] = OpConstant %[[#Int]] 4 {{$}}
; CHECK-DAG: %[[#MemSem_Release:]] = OpConstant %[[#Int]] 4{{$}}
; CHECK-DAG: %[[#MemSem_AcquireRelease:]] = OpConstant %[[#Int]] 8
; CHECK-DAG: %[[#MemSem_SequentiallyConsistent:]] = OpConstant %[[#Int]] 16
; CHECK-DAG: %[[#Value:]] = OpConstant %[[#Int]] 42
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/SPIRV/constant/local-integers-constants.ll
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Expand Up @@ -44,8 +44,8 @@ define i64 @getLargeConstantI64() {
; CHECK-DAG: %[[#CST_I8:]] = OpConstant %[[#I8]] 2
; CHECK-DAG: %[[#CST_I16:]] = OpConstant %[[#I16]] 65478
; CHECK-DAG: %[[#CST_I32:]] = OpConstant %[[#I32]] 42
; CHECK-DAG: %[[#CST_I64:]] = OpConstant %[[#I64]] 123456789 0
; CHECK-DAG: %[[#CST_LARGE_I64:]] = OpConstant %[[#I64]] 0 8
; CHECK-DAG: %[[#CST_I64:]] = OpConstant %[[#I64]] 123456789
; CHECK-DAG: %[[#CST_LARGE_I64:]] = OpConstant %[[#I64]] 34359738368

; CHECK: %[[#GET_I8]] = OpFunction %[[#I8]]
; CHECK: OpReturnValue %[[#CST_I8]]
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/SPIRV/lshr-constexpr.ll
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Expand Up @@ -5,7 +5,7 @@
; CHECK-SPIRV: %[[#type_vec:]] = OpTypeVector %[[#type_int32]] 2
; CHECK-SPIRV: %[[#const1:]] = OpConstant %[[#type_int32]] 1
; CHECK-SPIRV: %[[#vec_const:]] = OpConstantComposite %[[#type_vec]] %[[#const1]] %[[#const1]]
; CHECK-SPIRV: %[[#const32:]] = OpConstant %[[#type_int64]] 32 0
; CHECK-SPIRV: %[[#const32:]] = OpConstant %[[#type_int64]] 32

; CHECK-SPIRV: %[[#bitcast_res:]] = OpBitcast %[[#type_int64]] %[[#vec_const]]
; CHECK-SPIRV: %[[#shift_res:]] = OpShiftRightLogical %[[#type_int64]] %[[#bitcast_res]] %[[#const32]]
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll
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Expand Up @@ -41,10 +41,10 @@
; SPV-DAG: %[[#mone_16:]] = OpConstant %[[#int_16]] 65535
; SPV-DAG: %[[#mone_32:]] = OpConstant %[[#int_32]] 4294967295
; SPV-DAG: %[[#zero_64:]] = OpConstantNull %[[#int_64]]
; SPV-DAG: %[[#mone_64:]] = OpConstant %[[#int_64]] 4294967295 4294967295
; SPV-DAG: %[[#mone_64:]] = OpConstant %[[#int_64]] 18446744073709551615
; SPV-DAG: %[[#one_8:]] = OpConstant %[[#int_8]] 1
; SPV-DAG: %[[#one_16:]] = OpConstant %[[#int_16]] 1
; SPV-DAG: %[[#one_64:]] = OpConstant %[[#int_64]] 1 0
; SPV-DAG: %[[#one_64:]] = OpConstant %[[#int_64]] 1
; SPV-DAG: %[[#void:]] = OpTypeVoid
; SPV-DAG: %[[#float:]] = OpTypeFloat 32
; SPV-DAG: %[[#bool:]] = OpTypeBool
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