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[AArch64][GlobalISel] Fix miscompile on carry-in selection #68840

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Oct 19, 2023
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20 changes: 19 additions & 1 deletion llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -102,6 +102,11 @@ class AArch64InstructionSelector : public InstructionSelector {
// An early selection function that runs before the selectImpl() call.
bool earlySelect(MachineInstr &I);

/// Save state that is shared between select calls, call select on \p I and
/// then restore the saved state. This can be used to recursively call select
/// within a select call.
bool selectAndRestoreState(MachineInstr &I);

// Do some preprocessing of G_PHIs before we begin selection.
void processPHIs(MachineFunction &MF);

Expand Down Expand Up @@ -3552,6 +3557,13 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
return false;
}

bool AArch64InstructionSelector::selectAndRestoreState(MachineInstr &I) {
MachineIRBuilderState OldMIBState = MIB.getState();
bool Success = select(I);
MIB.getState() = std::move(OldMIBState);
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Just add a setState() instead? The state can be copied by value, it's just some pointers and an iterator.

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@tobias-stadler tobias-stadler Oct 18, 2023

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What about the DebugLoc? It has a TrackingMDRef, which does seem to benefit from moving, because it can call MetadataTracking::retrack(). Is it negligible? I don't understand the details of MetadataTracking.

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I'm also not familiar with that, but we already copy DebugLocs everywhere in llvm so I doubt think it's an issue?

return Success;
}

bool AArch64InstructionSelector::selectReduction(MachineInstr &I,
MachineRegisterInfo &MRI) {
Register VecReg = I.getOperand(1).getReg();
Expand Down Expand Up @@ -4749,11 +4761,17 @@ MachineInstr *AArch64InstructionSelector::emitCarryIn(MachineInstr &I,
// emit a carry generating instruction. E.g. for G_UADDE/G_USUBE sequences
// generated during legalization of wide add/sub. This optimization depends on
// these sequences not being interrupted by other instructions.
// We have to select the previous instruction before the carry-using
// instruction is deleted by the calling function, otherwise the previous
// instruction might become dead and would get deleted.
MachineInstr *SrcMI = MRI->getVRegDef(CarryReg);
if (SrcMI == I.getPrevNode()) {
if (auto *CarrySrcMI = dyn_cast<GAddSubCarryOut>(SrcMI)) {
bool ProducesNegatedCarry = CarrySrcMI->isSub();
if (NeedsNegatedCarry == ProducesNegatedCarry && CarrySrcMI->isUnsigned())
if (NeedsNegatedCarry == ProducesNegatedCarry &&
CarrySrcMI->isUnsigned() &&
CarrySrcMI->getCarryOutReg() == CarryReg &&
selectAndRestoreState(*SrcMI))
return nullptr;
}
}
Expand Down
31 changes: 31 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/select-sadde.mir
Original file line number Diff line number Diff line change
Expand Up @@ -175,3 +175,34 @@ body: |
$x2 = COPY %9(s64)
RET_ReallyLR implicit $x0, implicit $x1, implicit $x2
...
...
---
name: sadde_opt_prev_dead
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: sadde_opt_prev_dead
; CHECK: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x3
; CHECK-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY2]], implicit-def $nzcv
; CHECK-NEXT: [[ADCSXr:%[0-9]+]]:gpr64 = ADCSXr [[COPY1]], [[COPY3]], implicit-def $nzcv, implicit $nzcv
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%2:gpr(s64) = COPY $x2
%3:gpr(s64) = COPY $x3
%4:gpr(s64), %5:gpr(s32) = G_UADDO %0, %2
%6:gpr(s64), %7:gpr(s32) = G_SADDE %1, %3, %5
$w0 = COPY %7(s32)
RET_ReallyLR implicit $w0
...
31 changes: 31 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/select-ssube.mir
Original file line number Diff line number Diff line change
Expand Up @@ -175,3 +175,34 @@ body: |
$x2 = COPY %9(s64)
RET_ReallyLR implicit $x0, implicit $x1, implicit $x2
...
...
---
name: ssube_opt_prev_dead
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: ssube_opt_prev_dead
; CHECK: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x3
; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY2]], implicit-def $nzcv
; CHECK-NEXT: [[SBCSXr:%[0-9]+]]:gpr64 = SBCSXr [[COPY1]], [[COPY3]], implicit-def $nzcv, implicit $nzcv
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%2:gpr(s64) = COPY $x2
%3:gpr(s64) = COPY $x3
%4:gpr(s64), %5:gpr(s32) = G_USUBO %0, %2
%6:gpr(s64), %7:gpr(s32) = G_SSUBE %1, %3, %5
$w0 = COPY %7(s32)
RET_ReallyLR implicit $w0
...
31 changes: 31 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/select-uadde.mir
Original file line number Diff line number Diff line change
Expand Up @@ -175,3 +175,34 @@ body: |
$x2 = COPY %9(s64)
RET_ReallyLR implicit $x0, implicit $x1, implicit $x2
...
...
---
name: uadde_opt_prev_dead
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: uadde_opt_prev_dead
; CHECK: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x3
; CHECK-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY2]], implicit-def $nzcv
; CHECK-NEXT: [[ADCSXr:%[0-9]+]]:gpr64 = ADCSXr [[COPY1]], [[COPY3]], implicit-def $nzcv, implicit $nzcv
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%2:gpr(s64) = COPY $x2
%3:gpr(s64) = COPY $x3
%4:gpr(s64), %5:gpr(s32) = G_UADDO %0, %2
%6:gpr(s64), %7:gpr(s32) = G_UADDE %1, %3, %5
$w0 = COPY %7(s32)
RET_ReallyLR implicit $w0
...
31 changes: 31 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/select-usube.mir
Original file line number Diff line number Diff line change
Expand Up @@ -175,3 +175,34 @@ body: |
$x2 = COPY %9(s64)
RET_ReallyLR implicit $x0, implicit $x1, implicit $x2
...
...
---
name: usube_opt_prev_dead
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: usube_opt_prev_dead
; CHECK: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x3
; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY2]], implicit-def $nzcv
; CHECK-NEXT: [[SBCSXr:%[0-9]+]]:gpr64 = SBCSXr [[COPY1]], [[COPY3]], implicit-def $nzcv, implicit $nzcv
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1
%2:gpr(s64) = COPY $x2
%3:gpr(s64) = COPY $x3
%4:gpr(s64), %5:gpr(s32) = G_USUBO %0, %2
%6:gpr(s64), %7:gpr(s32) = G_USUBE %1, %3, %5
$w0 = COPY %7(s32)
RET_ReallyLR implicit $w0
...