Skip to content

Commit

Permalink
Merge
Browse files Browse the repository at this point in the history
  • Loading branch information
theaoqi committed Jan 29, 2024
2 parents b23c5bc + 26de9e2 commit 44a6530
Show file tree
Hide file tree
Showing 539 changed files with 15,592 additions and 6,188 deletions.
12 changes: 9 additions & 3 deletions bin/blessed-modifier-order.sh
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
#!/bin/bash
#
# Copyright (c) 2024, Oracle and/or its affiliates. All rights reserved.
# Copyright 2015 Google, Inc. All Rights Reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
Expand All @@ -26,12 +27,17 @@ usage() {
echo "$0 DIR ..."
echo "Modifies in place all the java source files found"
echo "in the given directories so that all java language modifiers"
echo "are in the canonical order given by Modifier#toString()."
echo "are in the canonical order."
echo "Tries to get it right even within javadoc comments,"
echo "and even if the list of modifiers spans 2 lines."
echo
echo "See:"
echo "https://docs.oracle.com/javase/8/docs/api/java/lang/reflect/Modifier.html#toString-int-"
echo "https://docs.oracle.com/javase/specs/jls/se21/html/jls-8.html#jls-8.1.1"
echo "https://docs.oracle.com/javase/specs/jls/se21/html/jls-8.html#jls-8.3.1"
echo "https://docs.oracle.com/javase/specs/jls/se21/html/jls-8.html#jls-8.4.3"
echo "https://docs.oracle.com/javase/specs/jls/se21/html/jls-8.html#jls-8.8.3"
echo "https://docs.oracle.com/javase/specs/jls/se21/html/jls-9.html#jls-9.1.1"
echo "https://docs.oracle.com/javase/specs/jls/se21/html/jls-9.html#jls-9.4"
echo
echo "Example:"
echo "$0 jdk/src/java.base jdk/test/java/{util,io,lang}"
Expand All @@ -46,7 +52,7 @@ for dir in "${dirs[@]}"; do [[ -d "$dir" ]] || usage; done

declare -ar modifiers=(
public protected private
abstract static final transient
abstract default static final sealed non-sealed transient
volatile synchronized native strictfp
)
declare -r SAVE_IFS="$IFS"
Expand Down
41 changes: 37 additions & 4 deletions make/jdk/src/classes/build/tools/cldrconverter/CLDRConverter.java
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2024, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -1289,25 +1289,58 @@ private static Map<Locale, String> coverageLevelsMap() throws Exception {
*/
private static void generateTZDBShortNamesMap() throws IOException {
Files.walk(Path.of(tzDataDir), 1, FileVisitOption.FOLLOW_LINKS)
.filter(p -> p.toFile().isFile())
.filter(p -> p.toFile().isFile() && !p.endsWith("jdk11_backward"))
.forEach(p -> {
try {
String zone = null;
String rule = null;
String format = null;
boolean inVanguard = false;
boolean inRearguard = false;
for (var line : Files.readAllLines(p)) {
if (line.contains("#STDOFF")) continue;
// Interpret the line in rearguard mode so that STD/DST
// correctly handles negative DST cases, such as "GMT/IST"
// vs. "IST/GMT" case for Europe/Dublin
if (inVanguard) {
if (line.startsWith("# Rearguard")) {
inVanguard = false;
inRearguard = true;
}
continue;
} else if (line.startsWith("# Vanguard")) {
inVanguard = true;
continue;
}
if (inRearguard) {
if (line.startsWith("# End of rearguard")) {
inRearguard = false;
continue;
} else {
if (line.startsWith("#\t")) {
line = line.substring(1); // omit #
}
}
}
if (line.isBlank() || line.matches("^[ \t]*#.*")) {
// ignore blank/comment lines
continue;
}
// remove comments in-line
line = line.replaceAll("[ \t]*#.*", "");

// Zone line
if (line.startsWith("Zone")) {
if (zone != null) {
tzdbShortNamesMap.put(zone, format + NBSP + rule);
}
var zl = line.split("[ \t]+", -1);
zone = zl[1];
rule = zl[3];
format = zl[4];
} else {
if (zone != null) {
if (line.isBlank()) {
if (line.startsWith("Rule") ||
line.startsWith("Link")) {
tzdbShortNamesMap.put(zone, format + NBSP + rule);
zone = null;
rule = null;
Expand Down
6 changes: 5 additions & 1 deletion make/test/BuildTestLibNative.gmk
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
#
# Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved.
# Copyright (c) 2020, 2024, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -45,6 +45,10 @@ BUILD_LIBTEST_OUTPUT_DIR := $(OUTPUTDIR)/support/test/lib/native

BUILD_LIBTEST_IMAGE_DIR := $(TEST_IMAGE_DIR)/lib

ifeq ($(call isTargetOs, windows), false)
BUILD_LIBTEST_LIBRARIES_EXCLUDE += libFileUtils.c
endif

# This evaluation is expensive and should only be done if this target was
# explicitly called.
ifneq ($(filter build-test-lib-native, $(MAKECMDGOALS)), )
Expand Down
7 changes: 6 additions & 1 deletion make/test/JtregNativeHotspot.gmk
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
#
# Copyright (c) 2015, 2023, Oracle and/or its affiliates. All rights reserved.
# Copyright (c) 2015, 2024, Oracle and/or its affiliates. All rights reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -857,6 +857,11 @@ else
exeinvoke.c exestack-gap.c exestack-tls.c libAsyncGetCallTraceTest.cpp
endif

ifeq ($(call And, $(call isTargetOs, linux) $(call isTargetCpu, aarch64)), false)
BUILD_HOTSPOT_JTREG_EXCLUDE += libTestSVEWithJNI.c
endif


BUILD_HOTSPOT_JTREG_EXECUTABLES_LIBS_exesigtest := -ljvm

ifeq ($(call isTargetOs, windows), true)
Expand Down
4 changes: 2 additions & 2 deletions src/demo/share/jfc/J2Ddemo/java2d/Intro.java
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
/*
*
* Copyright (c) 2007, 2018, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2007, 2024, Oracle and/or its affiliates. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
Expand Down Expand Up @@ -1716,7 +1716,7 @@ public Contributors(int beg, int end, Surface surf) {
this.beginning = beg;
this.ending = end;
fm = surf.getMetrics(font);
java.util.Arrays.sort(members);
Arrays.sort(members);
cast.add("CONTRIBUTORS");
cast.add(" ");
cast.addAll(Arrays.asList(members));
Expand Down
20 changes: 19 additions & 1 deletion src/hotspot/cpu/aarch64/aarch64.ad
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
//
// Copyright (c) 2003, 2023, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2003, 2024, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2014, 2021, Red Hat, Inc. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
Expand Down Expand Up @@ -8237,6 +8237,24 @@ instruct popCountL_mem(iRegINoSp dst, memory8 mem, vRegD tmp) %{
ins_pipe(pipe_class_default);
%}

// ============================================================================
// VerifyVectorAlignment Instruction

instruct verify_vector_alignment(iRegP addr, immL_positive_bitmaskI mask, rFlagsReg cr) %{
match(Set addr (VerifyVectorAlignment addr mask));
effect(KILL cr);
format %{ "verify_vector_alignment $addr $mask \t! verify alignment" %}
ins_encode %{
Label Lskip;
// check if masked bits of addr are zero
__ tst($addr$$Register, $mask$$constant);
__ br(Assembler::EQ, Lskip);
__ stop("verify_vector_alignment found a misaligned vector memory access");
__ bind(Lskip);
%}
ins_pipe(pipe_slow);
%}

// ============================================================================
// MemBar Instruction

Expand Down
5 changes: 3 additions & 2 deletions src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2000, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
Expand Down Expand Up @@ -282,7 +282,8 @@ void LIR_Assembler::osr_entry() {
__ bind(L);
}
#endif
__ ldp(r19, r20, Address(OSR_buf, slot_offset));
__ ldr(r19, Address(OSR_buf, slot_offset));
__ ldr(r20, Address(OSR_buf, slot_offset + BytesPerWord));
__ str(r19, frame_map()->address_for_monitor_lock(i));
__ str(r20, frame_map()->address_for_monitor_object(i));
}
Expand Down
2 changes: 0 additions & 2 deletions src/hotspot/cpu/aarch64/frame_aarch64.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -156,8 +156,6 @@
static void verify_deopt_original_pc( CompiledMethod* nm, intptr_t* unextended_sp);
#endif

const ImmutableOopMap* get_oop_map() const;

public:
// Constructors

Expand Down
18 changes: 2 additions & 16 deletions src/hotspot/cpu/aarch64/frame_aarch64.inline.hpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
Expand Down Expand Up @@ -195,7 +195,7 @@ inline bool frame::equal(frame other) const {
&& unextended_sp() == other.unextended_sp()
&& fp() == other.fp()
&& pc() == other.pc();
assert(!ret || ret && cb() == other.cb() && _deopt_state == other._deopt_state, "inconsistent construction");
assert(!ret || (cb() == other.cb() && _deopt_state == other._deopt_state), "inconsistent construction");
return ret;
}

Expand Down Expand Up @@ -359,20 +359,6 @@ inline int frame::sender_sp_ret_address_offset() {
return frame::sender_sp_offset - frame::return_addr_offset;
}

inline const ImmutableOopMap* frame::get_oop_map() const {
if (_cb == nullptr) return nullptr;
if (_cb->oop_maps() != nullptr) {
NativePostCallNop* nop = nativePostCallNop_at(_pc);
if (nop != nullptr && nop->displacement() != 0) {
int slot = ((nop->displacement() >> 24) & 0xff);
return _cb->oop_map_for_slot(slot, _pc);
}
const ImmutableOopMap* oop_map = OopMapSet::find_map(this);
return oop_map;
}
return nullptr;
}

//------------------------------------------------------------------------------
// frame::sender
inline frame frame::sender(RegisterMap* map) const {
Expand Down
4 changes: 4 additions & 0 deletions src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -42,8 +42,12 @@ const bool CCallingConventionRequiresIntsAsLongs = false;
// and Operational Models for ARMv8"
#define CPU_MULTI_COPY_ATOMIC

// The expected size in bytes of a cache line.
#define DEFAULT_CACHE_LINE_SIZE 64

// The default padding size for data structures to avoid false sharing.
#define DEFAULT_PADDING_SIZE DEFAULT_CACHE_LINE_SIZE

// According to the ARMv8 ARM, "Concurrent modification and execution
// of instructions can lead to the resulting instruction performing
// any behavior that can be achieved by executing any sequence of
Expand Down
13 changes: 9 additions & 4 deletions src/hotspot/cpu/aarch64/nativeInst_aarch64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -560,18 +560,23 @@ static bool is_movk_to_zr(uint32_t insn) {
}
#endif

void NativePostCallNop::patch(jint diff) {
bool NativePostCallNop::patch(int32_t oopmap_slot, int32_t cb_offset) {
if (((oopmap_slot & 0xff) != oopmap_slot) || ((cb_offset & 0xffffff) != cb_offset)) {
return false; // cannot encode
}
uint32_t data = ((uint32_t)oopmap_slot << 24) | cb_offset;
#ifdef ASSERT
assert(diff != 0, "must be");
assert(data != 0, "must be");
uint32_t insn1 = uint_at(4);
uint32_t insn2 = uint_at(8);
assert (is_movk_to_zr(insn1) && is_movk_to_zr(insn2), "must be");
#endif

uint32_t lo = diff & 0xffff;
uint32_t hi = (uint32_t)diff >> 16;
uint32_t lo = data & 0xffff;
uint32_t hi = data >> 16;
Instruction_aarch64::patch(addr_at(4), 20, 5, lo);
Instruction_aarch64::patch(addr_at(8), 20, 5, hi);
return true; // successfully encoded
}

void NativeDeoptInstruction::verify() {
Expand Down
14 changes: 9 additions & 5 deletions src/hotspot/cpu/aarch64/nativeInst_aarch64.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -691,16 +691,20 @@ class NativePostCallNop: public NativeInstruction {
return (insns & 0xffe0001fffffffff) == 0xf280001fd503201f;
}

jint displacement() const {
bool decode(int32_t& oopmap_slot, int32_t& cb_offset) const {
uint64_t movk_insns = *(uint64_t*)addr_at(4);
uint32_t lo = (movk_insns >> 5) & 0xffff;
uint32_t hi = (movk_insns >> (5 + 32)) & 0xffff;
uint32_t result = (hi << 16) | lo;

return (jint)result;
uint32_t data = (hi << 16) | lo;
if (data == 0) {
return false; // no information encoded
}
cb_offset = (data & 0xffffff);
oopmap_slot = (data >> 24) & 0xff;
return true; // decoding succeeded
}

void patch(jint diff);
bool patch(int32_t oopmap_slot, int32_t cb_offset);
void make_deopt();
};

Expand Down
4 changes: 2 additions & 2 deletions src/hotspot/cpu/arm/arm.ad
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
//
// Copyright (c) 2008, 2023, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2008, 2024, Oracle and/or its affiliates. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -9193,7 +9193,7 @@ instruct clear_array(iRegX cnt, iRegP base, iRegI temp, iRegX zero, Universe dum
ins_encode %{
__ mov($zero$$Register, 0);
__ mov($temp$$Register, $cnt$$Register);
Label(loop);
Label loop;
__ bind(loop);
__ subs($temp$$Register, $temp$$Register, 4);
__ str($zero$$Register, Address($base$$Register, $temp$$Register), ge);
Expand Down
4 changes: 2 additions & 2 deletions src/hotspot/cpu/arm/assembler_arm.hpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2008, 2024, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -175,7 +175,7 @@ class Address {
if (_index == noreg) {
assert(-256 < _disp && _disp < 256, "encoding constraint");
return _mode | up(_disp) << 23 | 1 << 22 | _base->encoding() << 16 |
(abs(_disp) & 0xf0) << 4 | abs(_disp) & 0x0f;
(abs(_disp) & 0xf0) << 4 | (abs(_disp) & 0x0f);
} else {
assert(_index != PC && (_mode == basic_offset || _index != _base), "unpredictable instruction");
assert(_disp == 0 && _shift == lsl && _shift_imm == 0, "encoding constraint");
Expand Down
6 changes: 3 additions & 3 deletions src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2008, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2008, 2024, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -2640,8 +2640,8 @@ void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* arg


void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
assert(src->is_double_cpu() && dest->is_address() ||
src->is_address() && dest->is_double_cpu(),
assert((src->is_double_cpu() && dest->is_address()) ||
(src->is_address() && dest->is_double_cpu()),
"Simple move_op is called for all other cases");

int null_check_offset;
Expand Down
2 changes: 0 additions & 2 deletions src/hotspot/cpu/arm/frame_arm.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -99,8 +99,6 @@
}
#endif

const ImmutableOopMap* get_oop_map() const;

public:
// Constructors

Expand Down
Loading

0 comments on commit 44a6530

Please sign in to comment.