Functional coverage for gpio straps

- Included new file gpio_cover.cfg to add the gpio_straps_if cover
assertions in the database
- Added the configuration file above into the gpio_sim_cfg.hjson
- Included the commit from PR: 25868 about straps verification,
from this point, only needs to review these files:
        - new file:   hw/ip/gpio/dv/cov/gpio_cover.cfg
        - modified:   hw/ip/gpio/dv/gpio_sim_cfg.hjson (Inclusion about
          the gpio_cover.cfg)
        - modified:   hw/ip/gpio/dv/env/gpio_env_cov.sv
        - new file:   hw/ip/gpio/dv/interfaces/gpio_straps_if.sv (New
          cover properties included)

Signed-off-by: Marcelo Carvalho Faleiro de Almeida <[email protected]>

hw/ip/gpio/dv/cov/gpio_cover.cfg

@@ -0,0 +1,6 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Enables the coverage for gpio_straps_if cover assertions.
++module gpio_straps_if

hw/ip/gpio/dv/env/gpio_env_pkg.sv

@@ -27,6 +27,7 @@ package gpio_env_pkg;
   parameter string LIST_OF_ALERTS[] = {"fatal_fault"};
 
   typedef virtual pins_if #(NUM_GPIOS) gpio_vif;
+  typedef virtual gpio_straps_if straps_vif;
   typedef class gpio_env_cfg;
   typedef class gpio_env_cov;
   typedef cip_base_virtual_sequencer #(gpio_env_cfg, gpio_env_cov) gpio_virtual_sequencer;

hw/ip/gpio/dv/gpio_sim_cfg.hjson

@@ -47,8 +47,15 @@
   // Add GPIO specific exclusion files.
   vcs_cov_excl_files: ["{proj_root}/hw/ip/gpio/dv/cov/gpio_cov_excl.el"]
 
+  overrides: [
+    {
+      name: default_vcs_cov_cfg_file
+      value: "-cm_hier {dv_root}/tools/vcs/cover.cfg+{proj_root}/hw/ip/gpio/dv/cov/gpio_cover.cfg"
+    }
+  ]
+
   // Enable cdc instrumentation.
-  run_opts: ["+cdc_instrumentation_enabled=1"]
+  run_opts: ["+cdc_instrumentation_enabled=1", "+interface", "+vcs+dumpinterface", "+define+UVM_DUMP_INTERFACES", "+cover=all"]
 
   // Add a second build mode to test the input synchronizers.
   // Note that since the scoreboard has a cycle accurate model
@@ -180,6 +187,10 @@
       build_mode: en_cdc_prims
       run_opts: ["+no_pullup_pulldown=1"]
     }
+    {
+      name: gpio_rand_straps
+      uvm_test_seq: gpio_rand_straps_vseq
+    }
   ]
 
   // List of regressions.

hw/ip/gpio/dv/interfaces/gpio_if.core

@@ -0,0 +1,18 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:gpio_if:0.1"
+description: "GPIO Interfaces"
+filesets:
+  files_dv:
+    depend:
+      - lowrisc:ip:gpio:0.1
+    files:
+      - gpio_straps_if.sv
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+      - files_dv

hw/ip/gpio/dv/interfaces/gpio_straps_if.sv

@@ -0,0 +1,63 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+// interface : gpio_straps_if
+`ifndef GPIO_STRAPS_IF_SV
+`define GPIO_STRAPS_IF_SV
+
+import gpio_pkg::*;
+
+// Interface definition
+interface gpio_straps_if();
+
+    logic          clk;
+    logic          rst_n;
+    logic          strap_en;       // Signal to enable straps
+    gpio_straps_t  sampled_straps; // Sampled gpio_i snapshot data from GPIO (DUT)
+
+    modport straps_port_in(input  clk,
+                           input  rst_n,
+                           input  strap_en,
+                           output sampled_straps);
+
+    modport straps_port_out(output  clk,
+                            output  rst_n,
+                            output  strap_en,
+                            input sampled_straps);
+
+    // Sequence to capture the timing relationship between strap_en and strap_data
+    sequence strap_data_timing_seq;
+        @(posedge clk) strap_en ##1 sampled_straps.data;
+    endsequence
+
+    // Property for the strap_data timing
+    property strap_data_timing_prop;
+        strap_data_timing_seq;
+    endproperty
+
+    // Cover the property
+    COV_STRAP_DATA_TIMING: cover property (strap_data_timing_prop);
+
+    // Sequence to capture the timing relationship between rst_n and strap_en
+    sequence reset_timing_seq;
+        @(posedge clk) rst_n ##1 strap_en;
+    endsequence
+
+    // Property for the reset timing
+    property reset_timing_prop;
+        reset_timing_seq;
+    endproperty
+
+    // Cover the property
+    COV_STRAP_RST_TIMING: cover property (reset_timing_prop);
+
+    // Additional checks for early strap_en
+    property strap_en_too_early_prop;
+        @(posedge clk) rst_n ##[1:$] strap_en;
+    endproperty
+
+    COV_STRAP_EN_TIMING: cover property (strap_en_too_early_prop);
+
+endinterface : gpio_straps_if
+
+`endif // GPIO_STRAPS_IF_SV

hw/ip/gpio/rtl/gpio.sv

@@ -85,7 +85,6 @@ module gpio
     assign hw2reg.hw_straps_data_in.d        = data_in_d;
     assign sampled_straps_o.data             = reg2hw.hw_straps_data_in.q;
     assign sampled_straps_o.valid            = reg2hw.hw_straps_data_in_valid.q;
-    `ASSUME(StrapSampleOnce_A, ##1 $fell(sample_trigger) |-> always !sample_trigger)
   end else begin : gen_no_strap_sample
     assign hw2reg.hw_straps_data_in_valid.de = 1'b0;
     assign hw2reg.hw_straps_data_in_valid.d  = 1'b0;