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[dd, aon_timer cov_closure] CCOV exclusion file for aon_timer
All the exclusions in this file are unreachable In addition, rtl exclusions added to config file Signed-off-by: Antonio Martinez Zambrana <[email protected]>
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hw/ip/aon_timer/dv/cov/aon_timer_unr_manually_excluded_excl.el
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,101 @@ | ||
| // Copyright lowRISC contributors (OpenTitan project). | ||
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. | ||
| // SPDX-License-Identifier: Apache-2.0 | ||
| // | ||
| //================================================== | ||
| // This file contains the Excluded objects | ||
| // Generated By User: antonio | ||
| // Format Version: 2 | ||
| // Date: Wed Dec 18 17:15:12 2024 | ||
| // ExclMode: default | ||
| //================================================== | ||
| CHECKSUM: "1706182284 132761700" | ||
| INSTANCE: tb.dut.u_reg.u_reg_if.u_rsp_intg_gen | ||
| ANNOTATION: "tl_i.d_user is hardcoded to 0x0 " | ||
| Block 1 "461445014" "assign rsp_intg = tl_i.d_user.rsp_intg;" | ||
| ANNOTATION: "tl_i.d_user is hardcoded to 0x0" | ||
| Block 2 "2643129081" "assign data_intg = tl_i.d_user.data_intg;" | ||
| CHECKSUM: "2815520955 1214062232" | ||
| INSTANCE: tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb | ||
| ANNOTATION: "Default statement can't be hit unless some wrong value is forced in the `state_d` signal" | ||
| Block 43 "3846199569" "gen_wr_req.state_d = StIdle;" | ||
| CHECKSUM: "2815520955 1214062232" | ||
| INSTANCE: tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb | ||
| ANNOTATION: "Default statement can't be hit unless some wrong value is forced in the `state_d` signal" | ||
| Block 43 "3846199569" "gen_wr_req.state_d = StIdle;" | ||
| CHECKSUM: "2815520955 1214062232" | ||
| INSTANCE: tb.dut.u_reg.u_wdog_count_cdc.u_arb | ||
| ANNOTATION: "Default statement can't be hit unless some wrong value is forced in the `state_d` signal" | ||
| Block 43 "3846199569" "gen_wr_req.state_d = StIdle;" | ||
| CHECKSUM: "2815520955 1214062232" | ||
| INSTANCE: tb.dut.u_reg.u_wkup_cause_cdc.u_arb | ||
| ANNOTATION: "Default statement can't be hit unless some wrong value is forced in the `state_d` signal" | ||
| Block 43 "3846199569" "gen_wr_req.state_d = StIdle;" | ||
| CHECKSUM: "2815520955 4051034043" | ||
| INSTANCE: tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb | ||
| ANNOTATION: "Default statement can't be hit unless some wrong value is forced in the `state_d` signal" | ||
| Branch 4 "3547459906" "gen_wr_req.state_q" (6) "gen_wr_req.state_q default,-,-,-,-" | ||
| CHECKSUM: "2815520955 4051034043" | ||
| INSTANCE: tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb | ||
| ANNOTATION: "Default statement can't be hit unless some wrong value is forced in the `state_d` signal" | ||
| Branch 4 "3547459906" "gen_wr_req.state_q" (6) "gen_wr_req.state_q default,-,-,-,-" | ||
| CHECKSUM: "2815520955 4051034043" | ||
| INSTANCE: tb.dut.u_reg.u_wdog_count_cdc.u_arb | ||
| ANNOTATION: "Default statement can't be hit unless some wrong value is forced in the `state_d` signal" | ||
| Branch 4 "3547459906" "gen_wr_req.state_q" (6) "gen_wr_req.state_q default,-,-,-,-" | ||
| CHECKSUM: "2815520955 4051034043" | ||
| INSTANCE: tb.dut.u_reg.u_wkup_cause_cdc.u_arb | ||
| ANNOTATION: "Default statement can't be hit unless some wrong value is forced in the `state_d` signal" | ||
| Branch 4 "3547459906" "gen_wr_req.state_q" (6) "gen_wr_req.state_q default,-,-,-,-" | ||
| CHECKSUM: "2815520955 4109606122" | ||
| INSTANCE: tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb | ||
| ANNOTATION: "It can't be hit because dst_update_ack won't be set prior to dst_update_req" | ||
| Condition 3 "3080886878" "(gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack) 1 -1" (1 "01") | ||
| CHECKSUM: "2815520955 4109606122" | ||
| INSTANCE: tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb | ||
| ANNOTATION: "It can't be hit because dst_update_ack won't be set prior to dst_update_req" | ||
| Condition 3 "3080886878" "(gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack) 1 -1" (1 "01") | ||
| ANNOTATION: "It can't be hit because the case where dst_req=1 and dst_lat_d=1 is covered in the branch above." | ||
| Condition 5 "593451913" "(((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d) 1 -1" (1 "01") | ||
| CHECKSUM: "2815520955 4109606122" | ||
| INSTANCE: tb.dut.u_reg.u_wdog_count_cdc.u_arb | ||
| ANNOTATION: "It can't be hit because dst_update_ack won't be set prior to dst_update_req" | ||
| Condition 3 "3080886878" "(gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack) 1 -1" (1 "01") | ||
| ANNOTATION: "It can't be hit because the case where dst_req=1 and dst_lat_d=1 is covered in the branch above." | ||
| Condition 5 "593451913" "(((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d) 1 -1" (1 "01") | ||
| CHECKSUM: "2815520955 4109606122" | ||
| INSTANCE: tb.dut.u_reg.u_wkup_cause_cdc.u_arb | ||
| ANNOTATION: "It can't be hit because dst_update_ack won't be set prior to dst_update_req" | ||
| Condition 3 "3080886878" "(gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack) 1 -1" (1 "01") | ||
| ANNOTATION: "It can't be hit because the case where dst_req=1 and dst_lat_d=1 is covered in the branch above." | ||
| Condition 5 "593451913" "(((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d) 1 -1" (1 "01") | ||
| CHECKSUM: "3643792208 1147758610" | ||
| INSTANCE: tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.u_dst_update_sync | ||
| ANNOTATION: "src_ack becomes one 1-cycle after dst_ack goes high. Since dst_ack_i is wired to dst_req_o, it means src_ack_o can't be set until after src_req_i is set." | ||
| Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") | ||
| ANNOTATION: "src_ack becomes one 1-cycle after dst_ack goes high. Since dst_ack_i is wired to dst_req_o, it means src_ack_o can't be set until after src_req_i is set." | ||
| Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") | ||
| ANNOTATION: "Output and input are connected to the same signal, hence the missing coverage is not reachable" | ||
| Condition 1 "1414883863" "(src_req_i & src_ack_o) 1 -1" (1 "01") | ||
| CHECKSUM: "3643792208 1147758610" | ||
| INSTANCE: tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.u_dst_update_sync | ||
| ANNOTATION: "src_ack becomes one 1-cycle after dst_ack goes high. Since dst_ack_i is wired to dst_req_o, it means src_ack_o can't be set until after src_req_i is set." | ||
| Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") | ||
| ANNOTATION: "src_ack becomes one 1-cycle after dst_ack goes high. Since dst_ack_i is wired to dst_req_o, it means src_ack_o can't be set until after src_req_i is set." | ||
| Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") | ||
| ANNOTATION: "Output and input are connected to the same signal, hence the missing coverage is not reachable" | ||
| Condition 1 "1414883863" "(src_req_i & src_ack_o) 1 -1" (1 "01") | ||
| CHECKSUM: "3643792208 1147758610" | ||
| INSTANCE: tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.u_dst_update_sync | ||
| ANNOTATION: "src_ack becomes one 1-cycle after dst_ack goes high. Since dst_ack_i is wired to dst_req_o, it means src_ack_o can't be set until after src_req_i is set." | ||
| Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") | ||
| ANNOTATION: "src_ack becomes one 1-cycle after dst_ack goes high. Since dst_ack_i is wired to dst_req_o, it means src_ack_o can't be set until after src_req_i is set." | ||
| Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") | ||
| ANNOTATION: "Output and input are connected to the same signal, hence the missing coverage is not reachable" | ||
| Condition 1 "1414883863" "(src_req_i & src_ack_o) 1 -1" (1 "01") | ||
| CHECKSUM: "3643792208 1147758610" | ||
| INSTANCE: tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync | ||
| ANNOTATION: "src_ack becomes one 1-cycle after dst_ack goes high. Since dst_ack_i is wired to dst_req_o, it means src_ack_o can't be set until after src_req_i is set." | ||
| Condition 1 "1414883863" "(src_req_i & src_ack_o) 1 -1" | ||
| ANNOTATION: "Output and input are connected to the same signal, hence the missing coverage is not reachable" | ||
| Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" |