adding monitoring subsystem final version

DE0_CV_VGA_Pattern.sdc

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+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -period 20 [get_ports CLOCK2_50]
+create_clock -period 20 [get_ports CLOCK3_50]
+create_clock -period 20 [get_ports CLOCK4_50]
+create_clock -period 20 [get_ports CLOCK_50]
+
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+##**************************************************************
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Load
+#**************************************************************

Forward_Buffer.vhd

@@ -0,0 +1,208 @@
+-- megafunction wizard: %FIFO%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: scfifo 
+
+-- ============================================================
+-- File Name: Forward_Buffer.vhd
+-- Megafunction Name(s):
+-- 			scfifo
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, the Altera Quartus Prime License Agreement,
+--the Altera MegaCore Function License Agreement, or other 
+--applicable license agreement, including, without limitation, 
+--that your use is for the sole purpose of programming logic 
+--devices manufactured by Altera and sold by Altera or its 
+--authorized distributors.  Please refer to the applicable 
+--agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY Forward_Buffer IS
+	PORT
+	(
+		aclr		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		rdreq		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		almost_full		: OUT STD_LOGIC ;
+		empty		: OUT STD_LOGIC ;
+		full		: OUT STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
+		usedw		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END Forward_Buffer;
+
+
+ARCHITECTURE SYN OF forward_buffer IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT scfifo
+	GENERIC (
+		add_ram_output_register		: STRING;
+		almost_full_value		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_numwords		: NATURAL;
+		lpm_showahead		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL;
+		lpm_widthu		: NATURAL;
+		overflow_checking		: STRING;
+		underflow_checking		: STRING;
+		use_eab		: STRING
+	);
+	PORT (
+			aclr	: IN STD_LOGIC ;
+			clock	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+			rdreq	: IN STD_LOGIC ;
+			wrreq	: IN STD_LOGIC ;
+			almost_full	: OUT STD_LOGIC ;
+			empty	: OUT STD_LOGIC ;
+			full	: OUT STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
+			usedw	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	almost_full    <= sub_wire0;
+	empty    <= sub_wire1;
+	full    <= sub_wire2;
+	q    <= sub_wire3(23 DOWNTO 0);
+	usedw    <= sub_wire4(7 DOWNTO 0);
+
+	scfifo_component : scfifo
+	GENERIC MAP (
+		add_ram_output_register => "OFF",
+		almost_full_value => 231,
+		intended_device_family => "Cyclone V",
+		lpm_numwords => 256,
+		lpm_showahead => "OFF",
+		lpm_type => "scfifo",
+		lpm_width => 24,
+		lpm_widthu => 8,
+		overflow_checking => "ON",
+		underflow_checking => "ON",
+		use_eab => "ON"
+	)
+	PORT MAP (
+		aclr => aclr,
+		clock => clock,
+		data => data,
+		rdreq => rdreq,
+		wrreq => wrreq,
+		almost_full => sub_wire0,
+		empty => sub_wire1,
+		full => sub_wire2,
+		q => sub_wire3,
+		usedw => sub_wire4
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "231"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "0"
+-- Retrieval info: PRIVATE: Depth NUMERIC "256"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "24"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "24"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+-- Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "231"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
+-- Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL "data[23..0]"
+-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
+-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
+-- Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+-- Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @data 0 0 24 0 data 0 0 24 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
+-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 24 0 @q 0 0 24 0
+-- Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Forward_Buffer.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Forward_Buffer.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Forward_Buffer.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Forward_Buffer.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Forward_Buffer_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf

MainRamMif.mif

@@ -0,0 +1,26 @@
+-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, the Altera Quartus Prime License Agreement,
+-- the Altera MegaCore Function License Agreement, or other 
+-- applicable license agreement, including, without limitation, 
+-- that your use is for the sole purpose of programming logic 
+-- devices manufactured by Altera and sold by Altera or its 
+-- authorized distributors.  Please refer to the applicable 
+-- agreement for further details.
+
+-- Quartus Prime generated Memory Initialization File (.mif)
+
+WIDTH=16;
+DEPTH=768;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+	[0..767]  :   65535;
+END;