Vectorize [Ifloatarithmem] #3452
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Currently it's always 8 but having this argument will help us consider alignment for new vector sequences.
and similar instructions
When the memory alignment is known to be 128-bit (currently, never) emits [addpd], otherwise emits a vector load followed by an arithmetic instruction.
Selection Change CheckThis PR modifies the original selection pass (targeting Mach). |
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On top of #3451.
There are two ways to vectorize
Ifloatarithmem, for example foradd` operation, we can eitherThis PR supports both options, although the more efficient one instruction cannot currently be emitted because we don't have the alignment guarantees. This can be enabled in the future if we propagate sufficient informaton about bigarrays for example, but may need runtime changes to ensure alignment.
To emit SIMD instructions with memory arguments, this PR adds a bunch of machinery to SIMD selection and handling to keep track of the addressing mode. In particular, it adds
ISimd_memto specific operations. The rest is trivial propagation of the new variant to all the right places. This is in a separate commit, which I am happy to split out into a separate PR if the design choices don't seem obvious. The new instructions are lightly tested manually (except for binary emitter), but are never emitted even when the vectorizer is enabled.