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PDP11: fix disassembly of reg,src instructions #331
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This corrects the disassembly of MUL, DIV, ASH, and ASHC so it works correctly when the register is not R0.
Hi Paul, |
How did you get 24 entries? I count 20. Remember that when you look at the "changed files" display it shows you the difference, so the red line is a deleted line and the green line is its replacement. |
6 lines with 4 entries each, makes 24. |
Ok, I misread the "changed file" display as if it were the whole table. |
Table had duplicate entries for more than a year. It should be: static const int32 masks[] = { The 24-entry table and this one are the same up until entry 15 (cond code set). The last four should be:
I broke it at the end of 2022, when I added FOPA, SOPA, SMDA to account for all the src -> dst floating point cases: 31-Dec-22 RMS Floating loads are src,dst (nickd4) and it got copied, verbatim, into V4. |
Thanks, @rms47!
Although, XOR is a RSOP operation (as well as JSR), 10. @pkoning2 , it looks like the version of the array that Bob says is correct does not agree with your patch... Can you please review and re-patch? |
True that. I checked that it worked for the EIS instructions and the fl ops that were added. |
@pkoning2 should I open another issue for this to be fixed? Thanks! |
@rms47 : I checked http://simh.trailing-edge.com/sources/current/PDP11/ and pdp11_sys.c is still not fixed there
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I just updated the whole directory. In addition to this fix, there are several interesting fixes to the Sigma, based on Ken Rector's ongoing work with diagnostics and exercisers. |
As discussed in PR#331, the fix needed more fix with the proper masks array. This patch completes the fix.
As discussed in PR#331, the fix needed more fix with the proper masks array. This patch completes the fix.
This corrects the disassembly of MUL, DIV, ASH, and ASHC so it works correctly when the register is not R0.