Skip to content

Commit

Permalink
3rd iteration of Z80 to Caravel mapping to minimise wires crossing on…
Browse files Browse the repository at this point in the history 
… PCB
  • Loading branch information
@rejunity
rejunity committed May 29, 2024
1 parent e01e28a commit bcd2685
Show file tree
Hide file tree
Showing 3 changed files with 76 additions and 33 deletions.
72 changes: 57 additions & 15 deletions src/ci2406_z80.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,6 @@ module ci2406_z80(
// <-- /IORQ |20 - io[4] 35 36 io[5] - 21| /RD -->
// `-------------------------------------'
//

// 2nd revised:
// ,----------------.___.----------------.
// <-- A11 |1 - io[19] 57 55 io[18] - 40| A10 -->
Expand All @@ -89,6 +88,30 @@ module ci2406_z80(
// <-- /IORQ |20 - io[35] 14<* * 34 io[3] - 21| /RD -->
// `-------------------------------------'
//
// 3rd revision:
// ,----------------.___.----------------.
// <-- A11 |1 - io[19] 57 55 io[18] - 40| A10 -->
// <-- A12 |2 - io[20] 58 54 io[17] - 39| A9 -->
// <-- A13 |3 - io[21] 59 53 io[16] - 38| A8 -->
// <-- A14 |4 - io[22] 60 51 io[15] - 37| A7 -->
// <-- A15 |5 - io[23] 61 50 io[14] - 36| A6 -->
// --> CLK |6 - xclk 22-- 48 io[13] - 35| A5 -->
// <-> D4 |7 - io[24] 62 * 42 io[8] - 34| A4 -->
// <-> D3 |8 - io[25] 2 * 43 io[9] - 33| A3 -->
// <-> D5 |9 - io[26] 3 44 io[10] - 32| A2 -->
// <-> D6 |10 - io[27] 4 * 46 io[12] - 31| A1 -->
// VCC_5V0 |11 * 45 io[11] - 30| A0 -->
// <-> D2 |12 - io[28] 5 29| GND
// <-> D7 |13 - io[29] 6 41 io[7] - 28| /RFSH -->
// <-> D0 |14 - io[31] 8 * --33 io[2] - 27| /M1 -->
// <-> D1 |15 - io[30] 7 * --21 rst - 26| /RESET <--
// --> /INT |16 - io[33] 12 * * 34 io[3] - 25| /BUSRQ <--
// --> /NMI |17 - io[32] 11 * * 37 io[6] - 24| /WAIT <--
// <-- /HALT |18 - io[0] 31-- --32 io[1] - 23| /BUSAK -->
// <-- /MREQ |19 - io[34] 13 * 36 io[5] - 22| /WR -->
// <-- /IORQ |20 - io[35] 14 * 35 io[4] - 21| /RD -->
// `-------------------------------------'

// GND 29 --- vss* [56,52,38,39,29,23,20,10,1]
// VCC_5V0 11 --- vddio [64,17]
// VCC_3V3 xx --- vdda1, vdda2 [47,40,30,9]
Expand All @@ -98,7 +121,7 @@ module ci2406_z80(
// @TODO: float A, D, MREQ, RD, WR, IORQ pins on BUSAK (Figure 10 BUS Request/Acknowledge Cycle)

// 8 output control pins
assign {io_oeb[35:34], io_oeb[7], io_oeb[4:0]}
assign {io_oeb[35:34], io_oeb[7], io_oeb[5:4], io_oeb[2:0]}
= { 8{1'b0}}; // 0 = Output

// 16 output address bus pins
Expand All @@ -108,18 +131,18 @@ module ci2406_z80(
assign io_oeb[31:24] = {8{~data_oe}};// 0 = Output | 1 = Input

// 4 input control pins
assign {io_oeb[33:32], io_oeb[6:5]} = { 4{1'b1}}; // 1 = Input
assign {io_out[33:32], io_out[6:5]} = { 4{1'b0}}; // Initialize otherwise undriven pins to 0
assign {io_oeb[33:32], io_oeb[6], io_oeb[3]} = {4{1'b1}}; // 1 = Input
assign {io_out[33:32], io_out[6], io_out[3]} = {4{1'b0}}; // Initialize otherwise undriven pins to 0

wire data_oe;
z80 z80 (
.clk (z80_clk),
.cen (ena),
.reset_n (rst_n),
.wait_n (io_in [ 5]),
.int_n (io_in [32]),
.nmi_n (io_in [33]),
.busrq_n (io_in [ 6]),
.wait_n (io_in [ 6]),
.int_n (io_in [33]),
.nmi_n (io_in [32]),
.busrq_n (io_in [ 3]),
// Z80 has peculiar data bus pin order, keep it to minimize wire crossing on the DIP40 PCB
// Also see: http://www.righto.com/2014/09/why-z-80s-data-pins-are-scrambled.html
// D7 - io[29]
Expand All @@ -128,19 +151,38 @@ module ci2406_z80(
// D4 - io[24]
// D3 - io[25]
// D2 - io[28]
// D1 - io[31]
// D0 - io[30]
.di ({io_in [29], io_in [27], io_in [26], io_in [24], io_in [25], io_in [28], io_in [31], io_in [30]}),
.dout ({io_out[29], io_out[27], io_out[26], io_out[24], io_out[25], io_out[28], io_out[31], io_out[30]}),
// D1 - io[30]
// D0 - io[31]
.di ({io_in [29], io_in [27], io_in [26], io_in [24], io_in [25], io_in [28], io_in [30], io_in [31]}),
.dout ({io_out[29], io_out[27], io_out[26], io_out[24], io_out[25], io_out[28], io_out[30], io_out[31]}),
.doe (data_oe),
.A (io_out[23:8]),

// io[23] - A15
// ...
// io[13] - A5
// io[8] - A4
// io[9] - A3
// io[10] - A2
// io[12] - A1
// io[11] - A0

.A ({io_out[23:13], io_out[8], io_out[9], io_out[10], io_out[12], io_out[11]}),

// 41 io[7] - 28| /RFSH -->
// 33 io[2] - 27| /M1 -->
// ...
// <-- /HALT |18 - io[0] io[1] - 23| /BUSAK -->
// <-- /MREQ |19 - io[34] io[5] - 22| /WR -->
// <-- /IORQ |20 - io[35] io[4] - 21| /RD -->
// `-------------------------------------'

.halt_n (io_out[ 0]),
.busak_n (io_out[ 1]),
.m1_n (io_out[ 2]),
.mreq_n (io_out[34]),
.iorq_n (io_out[35]),
.rd_n (io_out[ 3]),
.wr_n (io_out[ 4]),
.rd_n (io_out[ 4]),
.wr_n (io_out[ 5]),
.rfsh_n (io_out[ 7])
);
endmodule
Expand Down
22 changes: 11 additions & 11 deletions test_chipignite/tb.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -20,10 +20,10 @@ module tb ();
wire [35:0] io_oeb;

wire [3:0] controls_in;
wire [7:0] controls_out = {io_out[35:34], io_out[7], io_out[4:0]};
wire [15:0] addr = io_out[23:8];
wire [7:0] controls_out = {io_out[35:34], io_out[7], io_out[5:4], io_out[2:0]};
wire [15:0] addr = {io_out[23:13], io_out[8], io_out[9], io_out[10], io_out[12], io_out[11]};

assign {io_in [33:32], io_in [6:5]} = controls_in;
assign {io_in[33:32], io_in[6], io_in[3]} = controls_in;

// Z80 has a peculiar order of the pins for the data bus
// <-> D4 | io[24]
Expand All @@ -33,8 +33,8 @@ module tb ();
// VCC_5V0 |
// <-> D2 | io[28]
// <-> D7 | io[29]
// <-> D0 | io[30]
// <-> D1 | io[31]
// <-> D0 | io[31]
// <-> D1 | io[30]

wire [7:0] data_in;
wire [7:0] data_out;
Expand All @@ -46,26 +46,26 @@ module tb ();
assign io_in [27] = data_in[6];
assign io_in [28] = data_in[2];
assign io_in [29] = data_in[7];
assign io_in [30] = data_in[0];
assign io_in [31] = data_in[1];
assign io_in [31] = data_in[0];
assign io_in [30] = data_in[1];

assign data_out[4] = io_out[24];
assign data_out[3] = io_out[25];
assign data_out[5] = io_out[26];
assign data_out[6] = io_out[27];
assign data_out[2] = io_out[28];
assign data_out[7] = io_out[29];
assign data_out[0] = io_out[30];
assign data_out[1] = io_out[31];
assign data_out[0] = io_out[31];
assign data_out[1] = io_out[30];

assign data_oe [4] = ~io_oeb[24];
assign data_oe [3] = ~io_oeb[25];
assign data_oe [5] = ~io_oeb[26];
assign data_oe [6] = ~io_oeb[27];
assign data_oe [2] = ~io_oeb[28];
assign data_oe [7] = ~io_oeb[29];
assign data_oe [0] = ~io_oeb[30];
assign data_oe [1] = ~io_oeb[31];
assign data_oe [0] = ~io_oeb[31];
assign data_oe [1] = ~io_oeb[30];

// Replace tt_um_example with your module name:
ci2406_z80 user_project (
Expand Down
15 changes: 8 additions & 7 deletions test_chipignite/test.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,8 @@
from cocotb.clock import Clock
from cocotb.triggers import ClockCycles, FallingEdge, RisingEdge

BUS_READY = 0b1111 # not WAIT, not BUSRQ, not INT, not NMI
# io[3] io[6] io[32] io[33]
BUS_READY = 0b1111 # not BUSRQ, not WAIT, not INT, not NMI
OPCODE_NOP = 0x00
OPCODE_LDHL = 0x21
OPCODE_LDNNA = 0x32
Expand Down Expand Up @@ -150,17 +151,17 @@ async def start_and_reset(dut):
async def z80_step(z80, cycle, verbose=False):
def read_controls():
controls = [bit_n(z80.controls_out, n) for n in range(8)]
# | 41 io[7] - 28| /RFSH -->
# | 33 io[2] - 27| /M1 -->
# | io[7] - 28| /RFSH -->
# | io[2] - 27| /M1 -->
# | |
# | |
# | |
# <-- /HALT |18 - io[0] 31 32 io[1] - 23| /BUSAK -->
# <-- /MREQ |19 - io[34] 13 35 io[4] - 22| /WR -->
# <-- /IORQ |20 - io[35] 14 34 io[3] - 21| /RD -->
# <-- /HALT |18 - io[0] io[1] - 23| /BUSAK -->
# <-- /MREQ |19 - io[34] io[5] - 22| /WR -->
# <-- /IORQ |20 - io[35] io[4] - 21| /RD -->
# `-------------------------------------'
#
# io[0] io[1] io[2] io[3] io[4] io[7] io[34] io[35]
# io[0] io[1] io[2] io[4] io[5] io[7] io[34] io[35]
return dict(zip(['halt', 'busak', 'm1', 'rd', 'wr', 'rfsh', 'mreq', 'ioreq'], controls))

def read_data():
Expand Down

0 comments on commit bcd2685

Please sign in to comment.