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Pin revision, potentially less cross-over on the bottom part of the chip
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@rejunity
rejunity committed May 27, 2024
1 parent 288558f commit c97c09b
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Showing 3 changed files with 53 additions and 21 deletions.
59 changes: 44 additions & 15 deletions src/ci2406_z80.v
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Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,7 @@ module ci2406_z80(
// 2) Z80 data bus pin order is "scrambled"

// Z80 CPU
// 1st attempt:
// ,----------------.___.----------------.
// <-- A11 |1 - io[19] 57 55 io[18] - 40| A10 -->
// <-- A12 |2 - io[20] 58 54 io[17] - 39| A9 -->
Expand All @@ -63,6 +64,31 @@ module ci2406_z80(
// <-- /IORQ |20 - io[4] 35 36 io[5] - 21| /RD -->
// `-------------------------------------'
//

// 2nd revised:
// ,----------------.___.----------------.
// <-- A11 |1 - io[19] 57 55 io[18] - 40| A10 -->
// <-- A12 |2 - io[20] 58 54 io[17] - 39| A9 -->
// <-- A13 |3 - io[21] 59 53 io[16] - 38| A8 -->
// <-- A14 |4 - io[22] 60 51 io[15] - 37| A7 -->
// <-- A15 |5 - io[23] 61 >50 io[14] - 36| A6 -->
// --> CLK |6 - xclk 22-- >48 io[13] - 35| A5 -->
// <-> D4 |7 - io[24] 62< 46 io[12] - 34| A4 -->
// <-> D3 |8 - io[25] 2< 45 io[11] - 33| A3 -->
// <-> D5 |9 - io[26] 3 44 io[10] - 32| A2 -->
// <-> D6 |10 - io[27] 4 43 io[9] - 31| A1 -->
// VCC_5V0 |11 42 io[8] - 30| A0 -->
// <-> D2 |12 - io[28] 5 29| GND
// <-> D7 |13 - io[29] 6 41 io[7] - 28| /RFSH -->
// <-> D0 |14 - io[30] 7 --33 io[2] - 27| /M1 -->
// <-> D1 |15 - io[31] 8 --21 rst - 26| /RESET <--
// --> /INT |16 - io[32] 11 * 37 io[6] - 25| /BUSRQ <--
// --> /NMI |17 - io[33] 12 * 36 io[5] - 24| /WAIT <--
// <-- /HALT |18 - io[0] 31-- --32 io[1] - 23| /BUSAK -->
// <-- /MREQ |19 - io[34] 13 * * 35 io[4] - 22| /WR -->
// <-- /IORQ |20 - io[35] 14<* * 34 io[3] - 21| /RD -->
// `-------------------------------------'
//
// GND 29 --- vss* [56,52,38,39,29,23,20,10,1]
// VCC_5V0 11 --- vddio [64,17]
// VCC_3V3 xx --- vdda1, vdda2 [47,40,30,9]
Expand All @@ -72,25 +98,28 @@ module ci2406_z80(
// @TODO: float A, D, MREQ, RD, WR, IORQ pins on BUSAK (Figure 10 BUS Request/Acknowledge Cycle)

// 8 output control pins
assign io_oeb[7:0] = {8{1'b0}}; // 0 = Output
assign {io_oeb[35:34], io_oeb[7], io_oeb[4:0]}
= { 8{1'b0}}; // 0 = Output

// 16 output address bus pins
assign io_oeb[23:8] = {16{1'b0}}; // 0 = Output
assign io_oeb[23:8] = {16{1'b0}}; // 0 = Output

// 8 bidirectional data bus pins
assign io_oeb[31:24] = {8{~data_oe}};// 0 = Output | 1 = Input

assign io_oeb[31:24] = {8{~data_oe}}; // 0 = Output | 1 = Input
// 4 input control pins
assign io_oeb[35:32] = {4{1'b1}}; // 1 = Input
assign io_out[35:32] = {4{1'b0}}; // Initialize otherwise undriven pins to 0
assign {io_oeb[33:32], io_oeb[6:5]} = { 4{1'b1}}; // 1 = Input
assign {io_out[33:32], io_out[6:5]} = { 4{1'b0}}; // Initialize otherwise undriven pins to 0

wire data_oe;
z80 z80 (
.clk (z80_clk),
.cen (ena),
.reset_n (rst_n),
.wait_n (io_in [34]),
.wait_n (io_in [ 5]),
.int_n (io_in [32]),
.nmi_n (io_in [33]),
.busrq_n (io_in [35]),
.busrq_n (io_in [ 6]),
// Z80 has peculiar data bus pin order, keep it to minimize wire crossing on the DIP40 PCB
// Also see: http://www.righto.com/2014/09/why-z-80s-data-pins-are-scrambled.html
// D7 - io[29]
Expand All @@ -105,14 +134,14 @@ module ci2406_z80(
.dout ({io_out[29], io_out[27], io_out[26], io_out[24], io_out[25], io_out[28], io_out[31], io_out[30]}),
.doe (data_oe),
.A (io_out[23:8]),
.halt_n (io_out[0]),
.busak_n (io_out[1]),
.m1_n (io_out[2]),
.mreq_n (io_out[3]),
.iorq_n (io_out[4]),
.rd_n (io_out[5]),
.wr_n (io_out[6]),
.rfsh_n (io_out[7])
.halt_n (io_out[ 0]),
.busak_n (io_out[ 1]),
.m1_n (io_out[ 2]),
.mreq_n (io_out[34]),
.iorq_n (io_out[35]),
.rd_n (io_out[ 3]),
.wr_n (io_out[ 4]),
.rfsh_n (io_out[ 7])
);
endmodule

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4 changes: 2 additions & 2 deletions test_chipignite/tb.v
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Original file line number Diff line number Diff line change
Expand Up @@ -20,10 +20,10 @@ module tb ();
wire [35:0] io_oeb;

wire [3:0] controls_in;
wire [7:0] controls_out = io_out[7:0];
wire [7:0] controls_out = {io_out[35:34], io_out[7], io_out[4:0]};
wire [15:0] addr = io_out[23:8];

assign io_in [35:32] = controls_in;
assign {io_in [33:32], io_in [6:5]} = controls_in;

// Z80 has a peculiar order of the pins for the data bus
// <-> D4 | io[24]
Expand Down
11 changes: 7 additions & 4 deletions test_chipignite/test.py
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
from cocotb.clock import Clock
from cocotb.triggers import ClockCycles, FallingEdge, RisingEdge

BUS_READY = 0b1111 # not WAIT, not INT, not NMI, not BUSRQ
BUS_READY = 0b1111 # not WAIT, not BUSRQ, not INT, not NMI
OPCODE_NOP = 0x00
OPCODE_LDHL = 0x21
OPCODE_LDNNA = 0x32
Expand Down Expand Up @@ -150,16 +150,19 @@ async def start_and_reset(dut):
async def z80_step(z80, cycle, verbose=False):
def read_controls():
controls = [bit_n(z80.controls_out, n) for n in range(8)]
return dict(zip(['halt', 'busak', 'm1', 'mreq', 'ioreq', 'rd', 'wr', 'rfsh'], controls))
# | 41 io[7] - 28| /RFSH -->
# | 33 io[2] - 27| /M1 -->
# | |
# | |
# | |
# <-- /HALT |18 - io[0] 31 32 io[1] - 23| /BUSAK -->
# <-- /MREQ |19 - io[3] 34 37 io[6] - 22| /WR -->
# <-- /IORQ |20 - io[4] 35 36 io[5] - 21| /RD -->
# <-- /MREQ |19 - io[34] 13 35 io[4] - 22| /WR -->
# <-- /IORQ |20 - io[35] 14 34 io[3] - 21| /RD -->
# `-------------------------------------'
#
# io[0] io[1] io[2] io[3] io[4] io[7] io[34] io[35]
return dict(zip(['halt', 'busak', 'm1', 'rd', 'wr', 'rfsh', 'mreq', 'ioreq'], controls))

def read_data():
if z80.data_oe.value != 0b1111_1111:
return 'ZZ'
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