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rejunity / z80-open-silicon Public

generated from TinyTapeout/tt07-verilog-template

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gds

ChipIgnite QFN46 pin layout #47

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ChipIgnite QFN46 pin layout

ChipIgnite QFN46 pin layout #47

Summary
Jobs
- gds
- precheck
- gl_test
- viewer
Run details
- Usage
- Workflow file

Usage Workflow file

Annotations

2 errors and 1 warning

Process completed with exit code 1.

ENOENT: no such file or directory, open 'test/results.xml'

No files were found with the provided path: test/tb.vcd test/results.xml. No artifacts will be uploaded.

The logs for this run have expired and are no longer available.

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