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Updated VPWR/VGND ports inside GL_TEST to match new template tb.v gds #70: Commit 20368bb pushed by rejunity
November 8, 2024 21:35 16m 4s main
main
November 8, 2024 21:35 16m 4s
Updated VPWR/VGND ports inside GL_TEST to match new template tb.v gds #69: Commit 20368bb pushed by rejunity
November 8, 2024 21:18 15m 50s tt09
tt09
November 8, 2024 21:18 15m 50s
Docs: MUX pins gds #68: Commit 53d893b pushed by rejunity
November 8, 2024 20:52 16m 57s main
main
November 8, 2024 20:52 16m 57s
Docs: MUX pins gds #67: Commit 53d893b pushed by rejunity
November 3, 2024 10:05 17m 51s tt09
tt09
November 3, 2024 10:05 17m 51s
iHP0p2 new config.json with 0.75 density (upped from 70 just in case)… gds #66: Commit b33b073 pushed by rejunity
November 2, 2024 23:40 2h 18m 37s ttihp0p2
ttihp0p2
November 2, 2024 23:40 2h 18m 37s
The whole TT07 chip in OASIS format gds #65: Commit a8b2127 pushed by rejunity
November 2, 2024 23:24 16m 35s tt07-tapeout
tt07-tapeout
November 2, 2024 23:24 16m 35s
Update README.md gds #64: Commit 0d51915 pushed by rejunity
August 2, 2024 11:09 16m 4s main
main
August 2, 2024 11:09 16m 4s
Added recent DYI Z80 computer kits to list of good test-cases gds #63: Commit 5297295 pushed by rejunity
July 31, 2024 13:40 16m 44s main
main
July 31, 2024 13:40 16m 44s
CI2406 tapeout GDS gds #62: Commit 4f2ab29 pushed by rejunity
June 10, 2024 07:06 16m 2s ci2406
ci2406
June 10, 2024 07:06 16m 2s
Fixed stupid dangerous mistake in io_out initialisation! (introduced … gds #61: Commit 51fefd5 pushed by rejunity
June 6, 2024 14:42 16m 16s ci2406
ci2406
June 6, 2024 14:42 16m 16s
Separated early signal control lines gds #60: Commit c5312d6 pushed by rejunity
June 6, 2024 14:34 17m 58s ci2406
ci2406
June 6, 2024 14:34 17m 58s
WR is always normal. Custom settings to prolong MREQ & IORQ. gds #59: Commit d22bcf7 pushed by rejunity
June 6, 2024 14:25 24m 38s ci2406
ci2406
June 6, 2024 14:25 24m 38s
Optional half cycle earlier MREQ, IORQ, RD, WR signals gds #58: Commit f802101 pushed by rejunity
June 5, 2024 14:49 15m 25s ci2406
ci2406
June 5, 2024 14:49 15m 25s
Enalbed TV80_REFRESH gds #57: Commit 3c2be84 pushed by rejunity
June 5, 2024 12:19 17m 19s ci2406
ci2406
June 5, 2024 12:19 17m 19s
Enalbed TV80_REFRESH gds #56: Commit d3a7953 pushed by rejunity
June 5, 2024 12:01 16m 15s main
main
June 5, 2024 12:01 16m 15s
Fix stupid gds #55: Commit 9436cbd pushed by rejunity
June 5, 2024 10:55 16m 28s ci2406
ci2406
June 5, 2024 10:55 16m 28s
5th iteration of Z80 to Caravel mapping. gds #54: Commit a31522c pushed by rejunity
June 5, 2024 10:49 15m 54s ci2406
ci2406
June 5, 2024 10:49 15m 54s
Prep for CI2406 gds #53: Commit e034540 pushed by rejunity
June 4, 2024 07:46 16m 5s main
main
June 4, 2024 07:46 16m 5s
Made output mux asynchronous (non-clocked) and driven by excternal input gds #52: Commit 7f155e9 pushed by rejunity
June 1, 2024 18:38 15m 49s main
main
June 1, 2024 18:38 15m 49s
3rd iteration of Z80 to Caravel mapping to minimise wires crossing on… gds #51: Commit bcd2685 pushed by rejunity
May 30, 2024 06:34 16m 22s ci2406
ci2406
May 30, 2024 06:34 16m 22s
Whitespace gds #50: Commit e01e28a pushed by rejunity
May 27, 2024 23:22 16m 4s ci2406
ci2406
May 27, 2024 23:22 16m 4s
Pin revision, potentially less cross-over on the bottom part of the chip gds #49: Commit c97c09b pushed by rejunity
May 27, 2024 23:18 16m 0s ci2406
ci2406
May 27, 2024 23:18 16m 0s
Databus mapping in the weird z80 way (to reduce wires crossing) gds #48: Commit 288558f pushed by rejunity
May 27, 2024 19:58 15m 42s ci2406
ci2406
May 27, 2024 19:58 15m 42s
ChipIgnite QFN46 pin layout gds #47: Commit 3956114 pushed by rejunity
May 27, 2024 19:21 15m 37s ci2406
ci2406
May 27, 2024 19:21 15m 37s
Test for chipignite gds #46: Commit 79b4450 pushed by rejunity
May 27, 2024 14:51 16m 10s ci2406
ci2406
May 27, 2024 14:51 16m 10s