fix SpiBus::transfer logic

riscv-rust · Jun 23, 2022 · c7e37ab · c7e37ab
1 parent 648aa58
commit c7e37ab
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/spi/bus.rs b/src/spi/bus.rs
@@ -132,7 +132,7 @@ where
         self.wait_for_rxfifo();
 
         while iwrite < write.len() || iread < read.len() {
-            if iread < read.len() && self.spi.txdata.read().full().bit_is_clear() {
+            if iwrite < write.len() && self.spi.txdata.read().full().bit_is_clear() {
                 let byte = write.get(iwrite).unwrap_or(&0);
                 iwrite += 1;
                 self.spi.txdata.write(|w| unsafe { w.data().bits(*byte) });