Add Zicfilp codes (#225)

riscv · Feb 3, 2024 · f51aa42 · f51aa42
1 parent eb90130
commit f51aa42
Show file tree

Hide file tree

Showing 3 changed files with 6 additions and 0 deletions.
diff --git a/constants.py b/constants.py
@@ -220,6 +220,7 @@
     'mop_rr_7',
     'sspush_x1',
     'sspush_x5',
+    'lpad',
     'bclri.rv32',
     'bexti.rv32',
     'binvi.rv32',

diff --git a/encoding.h b/encoding.h
@@ -337,6 +337,9 @@
 #define SRMCFG_RCID  0x00000FFF
 #define SRMCFG_MCID  0x0FFF0000
 
+/* software check exception xtval codes */
+#define LANDING_PAD_FAULT 2
+
 #ifdef __riscv
 
 #if __riscv_xlen == 64

diff --git a/unratified/rv_zicfilp b/unratified/rv_zicfilp
@@ -0,0 +1,2 @@
+# auipc x0 imm20 -> lpad imm20
+$pseudo_op rv_i::auipc lpad imm20 11..7=0 6..2=0x05 1..0=3
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1,2 @@
		# auipc x0 imm20 -> lpad imm20
		$pseudo_op rv_i::auipc lpad imm20 11..7=0 6..2=0x05 1..0=3