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Assumptions about medeleg WARL behavior #17
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This is a duplicate of #12 but since it has substantially more information about what the problem is, I'll leave it open. |
I think it's OK to remove the |
The tests that fail are either buggy, or need to be conditioned on the implementation of the particular bit - which is something that the v.2 framework is supposed to deal with. But, the framework expects to filter tests, and the macros defined here are not part of any test, so that won't apply. We can remove the bne, but we will need write separate copies of any test that then fails (with uses all possible alternate WARL definitions), or be able to write a universal test that is passed a mask parameter (derived from the YAML). |
Of medeleg, the architecture says "An implementation can choose to subset the delegatable traps, with the supported delegatable bits found by writing one to every bit location, then reading back the value in medeleg or mideleg to see which bit positions hold a one." Presumably, an implementation can hard-wire medeleg to 0.
The spec also says "For exceptions that cannot occur in less privileged modes, the corresponding medeleg bits should be hardwired to zero." That means that in implementations that have misa.C hard-wired to 1, medeleg[0] is not only allowed to be hard-wired to 0 (as all bits are) but it is encouraged to be hard-wired to 0.
In riscv_test.h:
This means that (if it's not an M-mode-only implementation) those 6 traps must be delegatable to S mode or else it goes to
other_exception
("some unhandlable exception occurred"). This reset code should make no assumptions about the delegatability of traps in medeleg, especially misaligned fetches.This reset code assumption will cause the riscv-tests csr.S test to fail if, for example, misaligned fetches are not delegatable due to misa.C=1 (although presence or absence of C support is not otherwise necessary to run that test).
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