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@kasanovic
kasanovic committed Feb 1, 2019
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243 changes: 131 additions & 112 deletions inst-table.adoc
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Original file line number Diff line number Diff line change
@@ -1,99 +1,14 @@
.Vector Unit-Stride Load/Store Instruction Listing
[width="100%",cols="^3,^3,^3,^4,^4,^3,^3,^3,^7,<10"]
|========================
|31 30 |29 27 |26 25 |24 20 |19 15 |14 12 |11 10 |9 7 |6 0 |Opcode

|off[1:0]|000|vm|00000|rs1|000 2+|vd|0000111|VLBU.V
|off[1:0]|000|vm|00000|rs1|101 2+|vd|0000111|VLHU.V
|off[1:0]|000|vm|00000|rs1|110 2+|vd|0000111|VLWU.V
|off[1:0]|000|vm|00000|rs1|111 2+|vd|0000111|VLE.V
|off[1:0]|100|vm|00000|rs1|000 2+|vd|0000111|VLB.V
|off[1:0]|100|vm|00000|rs1|101 2+|vd|0000111|VLH.V
|off[1:0]|100|vm|00000|rs1|110 2+|vd|0000111|VLW.V
2+|vs3|vm|00000|rs1|000|off[1:0]|000|0100111|VSB.V
2+|vs3|vm|00000|rs1|101|off[1:0]|000|0100111|VSH.V
2+|vs3|vm|00000|rs1|110|off[1:0]|000|0100111|VSW.V
2+|vs3|vm|00000|rs1|111|off[1:0]|000|0100111|VSE.V
|========================


.Vector Unit-Stride Fault-First Load Instruction Listing
[width="100%",cols="^3,^3,^3,^4,^4,^3,^3,^3,^7,<10"]
|========================
|31 30 |29 27 |26 25 |24 20 |19 15 |14 12 |11 10 |9 7 |6 0 |Opcode

|off[1:0]|000|vm|10000|rs1|000 2+|vd|0000111|VLBUFF.V
|off[1:0]|000|vm|10000|rs1|101 2+|vd|0000111|VLHUFF.V
|off[1:0]|000|vm|10000|rs1|110 2+|vd|0000111|VLWUFF.V
|off[1:0]|000|vm|10000|rs1|111 2+|vd|0000111|VLEFF.V
|off[1:0]|100|vm|10000|rs1|000 2+|vd|0000111|VLBFF.V
|off[1:0]|100|vm|10000|rs1|101 2+|vd|0000111|VLHFF.V
|off[1:0]|100|vm|10000|rs1|110 2+|vd|0000111|VLWFF.V

|========================

.Vector Strided Load/Store Instruction Listing
[width="100%",cols="^3,^3,^3,^4,^4,^3,^3,^3,^7,<10"]
|========================
|31 30 |29 27 |26 25 |24 20 |19 15 |14 12 |11 10 |9 7 |6 0 |Opcode

|off[1:0]|010|vm|rs2|rs1|000 2+|vd|0000111|VLSBU.V
|off[1:0]|010|vm|rs2|rs1|101 2+|vd|0000111|VLSHU.V
|off[1:0]|010|vm|rs2|rs1|110 2+|vd|0000111|VLSWU.V
|off[1:0]|010|vm|rs2|rs1|111 2+|vd|0000111|VLSE.V
|off[1:0]|110|vm|rs2|rs1|000 2+|vd|0000111|VLSB.V
|off[1:0]|110|vm|rs2|rs1|101 2+|vd|0000111|VLSH.V
|off[1:0]|110|vm|rs2|rs1|110 2+|vd|0000111|VLSW.V
2+|vs3|vm|rs2|rs1|000|off[1:0]|010|0100111|VSSB.V
2+|vs3|vm|rs2|rs1|101|off[1:0]|010|0100111|VSSH.V
2+|vs3|vm|rs2|rs1|110|off[1:0]|010|0100111|VSSW.V
2+|vs3|vm|rs2|rs1|111|off[1:0]|010|0100111|VSSE.V

|========================


.Vector Indexed Load/Store Instruction Listing
[width="100%",cols="^3,^3,^3,^4,^4,^3,^3,^3,^7,<10"]
|========================
|31 30 |29 27 |26 25 |24 20 |19 15 |14 12 |11 10 |9 7 |6 0 |Opcode

|off[1:0]|011|vm|vs2|rs1|000 2+|vd|0000111|VLXBU.V
|off[1:0]|011|vm|vs2|rs1|101 2+|vd|0000111|VLXHU.V
|off[1:0]|011|vm|vs2|rs1|110 2+|vd|0000111|VLXWU.V
|off[1:0]|011|vm|vs2|rs1|111 2+|vd|0000111|VLXE.V
|off[1:0]|111|vm|vs2|rs1|000 2+|vd|0000111|VLXB.V
|off[1:0]|111|vm|vs2|rs1|101 2+|vd|0000111|VLXH.V
|off[1:0]|111|vm|vs2|rs1|110 2+|vd|0000111|VLXW.V
2+|vs3|vm|vs2|rs1|000|off[1:0]|011|0100111|VSXB.V
2+|vs3|vm|vs2|rs1|101|off[1:0]|011|0100111|VSXH.V
2+|vs3|vm|vs2|rs1|110|off[1:0]|011|0100111|VSXW.V
2+|vs3|vm|vs2|rs1|111|off[1:0]|011|0100111|VSXE.V
2+|vs3|vm|vs2|rs1|000|off[1:0]|111|0100111|VSUXB.V
2+|vs3|vm|vs2|rs1|101|off[1:0]|111|0100111|VSUXH.V
2+|vs3|vm|vs2|rs1|110|off[1:0]|111|0100111|VSUXW.V
2+|vs3|vm|vs2|rs1|111|off[1:0]|111|0100111|VSUXE.V

|========================


.Vector Table
[width="100%",cols="^3,^3,^3,^4,^4,^3,^3,^3,^7,<10"]
|========================
2+|31 27|26 25 |24 20 |19 15 |14 12 2+|11 7 |6 0 |Opcode

2+|00000|vm |vs2 |vs1 |001 2+|vd |1010111|VADD.VV
2+|00000|vm |vs2 |vs1 |000 2+|vd |1010111|VADD.VS
2+|00000|vm |vs2 |rs1 |010 2+|vd |1010111|VADD.VX
2+|00000|vm |vs2 |simm[4:0]|011 2+|vd |1010111|VADD.VI
|========================

[source]
----
Integer Integer FP
OPIVV V OPMVV V OPFVV V
funct3 funct3 funct3
OPIVV V OPMVV V OPFVV V
OPIVX X OPMVX X OPFVF F
OPIVI I
funct6 funct6 funct6
000000 VXI vadd 000000 V vredsum 000000 VF vfadd
000001 VX vsub 000001 V vredand 000001 VF vfsub
000010 000010 V vredor 000010 V vfredsum
Expand Down Expand Up @@ -136,32 +51,35 @@ OPIVI I
100101 VXI vsle 100101 100101 F vfgt
100110 XI vsgtu 100110 100110
100111 XI vsgt 100111 100111 F vfgte
101000 VXI vadc 101000 X vext.x.v 101000 V vfdot
101000 VXI vadc 101000 X vext.x.v 101000
101001 VXI vsbc 101001 X vins.v.x 101001
101010 101010 V vmv.x.s 101010 V vfmv.f.s
101011 101011 X vmv.s.x 101011 F vfmv.s.f
101100 VX vmulhu 101100 101100
101101 VX vmul 101101 101101
101110 VX vmulhsu 101110 101110
101111 VX vmulh 101111 101111

110000 110000 VX vdivu 110000 VF vfmadd
110001 VX vmadd 110001 VX vdiv 110001 VF vfnmadd
110010 110010 VX vremu 110010 VF vfmsub
110011 VX vmsub 110011 VX vrem 110011 VF vfnmsub
110100 110100 110100 VF vfmacc
110101 VX vmacc 110101 V vdot 110101 VF vfnmacc
110110 110110 110110 VF vfmsac
110111 VX vmsac 110111 110111 VF vfnmsac
111000 VX vwmulu 111000 111000 VF vfwmul
111001 111001 111001
101100 101100 101100
101101 101101 101101
101110 101110 101110
101111 101111 101111
110000 VX vmulhu 110000 110000 VF vfmadd
110001 VX vmul 110001 VX vmadd 110001 VF vfnmadd
110010 VX vmulhsu 110010 110010 VF vfmsub
110011 VX vmulh 110011 VX vmsub 110011 VF vfnmsub
110100 VX vdivu 110100 110100 VF vfmacc
110101 VX vdiv 110101 VX vmacc 110101 VF vfnmacc
110110 VX vremu 110110 110110 VF vfmsac
110111 VX vrem 110111 VX vmsac 110111 VF vfnmsac
111000 VX vwmulu 111000 V vdotu 111000 VF vfwmul
111001 111001 V vdot 111001 V vfdot
111010 VX vwmulsu 111010 111010
111011 VX vwmul 111011 111011 V vfwdot
111100 VX vwmaccu 111100 V vwdotu 111100 VF vfwmacc
111101 VX vwmacc 111101 V vwdot 111101 VF vfwnmacc
111110 VX vwmsacu 111110 V vw4dotu 111110 VF vfwmsac
111111 VX vwmsac 111111 V vw4dot 111111 VF vfwnmsac

111011 VX vwmul 111011 111011
111100 VX vwmaccu 111100 111100 VF vfwmacc
111101 VX vwmacc 111101 111101 VF vfwnmacc
111110 VX vwmsacu 111110 111110 VF vfwmsac
111111 VX vwmsac 111111 111111 VF vfwnmsac
----

[source]
----
VFUNARY0 encoding space
rs1
single-width converts
Expand All @@ -183,21 +101,110 @@ VFUNARY0 encoding space
10010 vfncvt.f.xu.v
10011 vfncvt.f.x.v
10100 vfncvt.f.f.v
----

[source]
----
VFUNARY1 encoding space
rs1
00000 vfsqrt.v
10000 vfclass.v
----

[source]
----
VMUNARY0 encoding space
rs1
00001 vmsbf
00010 vmsof
00011 vmsif
10000 vmiota
10001 vid
----


////
.Vector Unit-Stride Load/Store Instruction Listing
[width="100%",cols="^3,^3,^3,^4,^4,^3,^3,^3,^7,<10"]
|========================
|31 30 |29 27 |26 25 |24 20 |19 15 |14 12 |11 10 |9 7 |6 0 |Opcode

|off[1:0]|000|vm|00000|rs1|000 2+|vd|0000111|VLBU.V
|off[1:0]|000|vm|00000|rs1|101 2+|vd|0000111|VLHU.V
|off[1:0]|000|vm|00000|rs1|110 2+|vd|0000111|VLWU.V
|off[1:0]|000|vm|00000|rs1|111 2+|vd|0000111|VLE.V
|off[1:0]|100|vm|00000|rs1|000 2+|vd|0000111|VLB.V
|off[1:0]|100|vm|00000|rs1|101 2+|vd|0000111|VLH.V
|off[1:0]|100|vm|00000|rs1|110 2+|vd|0000111|VLW.V
2+|vs3|vm|00000|rs1|000|off[1:0]|000|0100111|VSB.V
2+|vs3|vm|00000|rs1|101|off[1:0]|000|0100111|VSH.V
2+|vs3|vm|00000|rs1|110|off[1:0]|000|0100111|VSW.V
2+|vs3|vm|00000|rs1|111|off[1:0]|000|0100111|VSE.V
|========================


.Vector Unit-Stride Fault-First Load Instruction Listing
[width="100%",cols="^3,^3,^3,^4,^4,^3,^3,^3,^7,<10"]
|========================
|31 30 |29 27 |26 25 |24 20 |19 15 |14 12 |11 10 |9 7 |6 0 |Opcode

|off[1:0]|000|vm|10000|rs1|000 2+|vd|0000111|VLBUFF.V
|off[1:0]|000|vm|10000|rs1|101 2+|vd|0000111|VLHUFF.V
|off[1:0]|000|vm|10000|rs1|110 2+|vd|0000111|VLWUFF.V
|off[1:0]|000|vm|10000|rs1|111 2+|vd|0000111|VLEFF.V
|off[1:0]|100|vm|10000|rs1|000 2+|vd|0000111|VLBFF.V
|off[1:0]|100|vm|10000|rs1|101 2+|vd|0000111|VLHFF.V
|off[1:0]|100|vm|10000|rs1|110 2+|vd|0000111|VLWFF.V

|========================

.Vector Strided Load/Store Instruction Listing
[width="100%",cols="^3,^3,^3,^4,^4,^3,^3,^3,^7,<10"]
|========================
|31 30 |29 27 |26 25 |24 20 |19 15 |14 12 |11 10 |9 7 |6 0 |Opcode

|off[1:0]|010|vm|rs2|rs1|000 2+|vd|0000111|VLSBU.V
|off[1:0]|010|vm|rs2|rs1|101 2+|vd|0000111|VLSHU.V
|off[1:0]|010|vm|rs2|rs1|110 2+|vd|0000111|VLSWU.V
|off[1:0]|010|vm|rs2|rs1|111 2+|vd|0000111|VLSE.V
|off[1:0]|110|vm|rs2|rs1|000 2+|vd|0000111|VLSB.V
|off[1:0]|110|vm|rs2|rs1|101 2+|vd|0000111|VLSH.V
|off[1:0]|110|vm|rs2|rs1|110 2+|vd|0000111|VLSW.V
2+|vs3|vm|rs2|rs1|000|off[1:0]|010|0100111|VSSB.V
2+|vs3|vm|rs2|rs1|101|off[1:0]|010|0100111|VSSH.V
2+|vs3|vm|rs2|rs1|110|off[1:0]|010|0100111|VSSW.V
2+|vs3|vm|rs2|rs1|111|off[1:0]|010|0100111|VSSE.V

|========================


.Vector Indexed Load/Store Instruction Listing
[width="100%",cols="^3,^3,^3,^4,^4,^3,^3,^3,^7,<10"]
|========================
|31 30 |29 27 |26 25 |24 20 |19 15 |14 12 |11 10 |9 7 |6 0 |Opcode

|off[1:0]|011|vm|vs2|rs1|000 2+|vd|0000111|VLXBU.V
|off[1:0]|011|vm|vs2|rs1|101 2+|vd|0000111|VLXHU.V
|off[1:0]|011|vm|vs2|rs1|110 2+|vd|0000111|VLXWU.V
|off[1:0]|011|vm|vs2|rs1|111 2+|vd|0000111|VLXE.V
|off[1:0]|111|vm|vs2|rs1|000 2+|vd|0000111|VLXB.V
|off[1:0]|111|vm|vs2|rs1|101 2+|vd|0000111|VLXH.V
|off[1:0]|111|vm|vs2|rs1|110 2+|vd|0000111|VLXW.V
2+|vs3|vm|vs2|rs1|000|off[1:0]|011|0100111|VSXB.V
2+|vs3|vm|vs2|rs1|101|off[1:0]|011|0100111|VSXH.V
2+|vs3|vm|vs2|rs1|110|off[1:0]|011|0100111|VSXW.V
2+|vs3|vm|vs2|rs1|111|off[1:0]|011|0100111|VSXE.V
2+|vs3|vm|vs2|rs1|000|off[1:0]|111|0100111|VSUXB.V
2+|vs3|vm|vs2|rs1|101|off[1:0]|111|0100111|VSUXH.V
2+|vs3|vm|vs2|rs1|110|off[1:0]|111|0100111|VSUXW.V
2+|vs3|vm|vs2|rs1|111|off[1:0]|111|0100111|VSUXE.V

|========================
////



////

X vsgteu
X vsgte
Expand All @@ -207,6 +214,17 @@ vx4muladd
vx4mulsub


.Vector Table
[width="100%",cols="^3,^3,^3,^4,^4,^3,^3,^3,^7,<10"]
|========================
2+|31 27|26 25 |24 20 |19 15 |14 12 2+|11 7 |6 0 |Opcode

2+|00000|vm |vs2 |vs1 |001 2+|vd |1010111|VADD.VV
2+|00000|vm |vs2 |vs1 |000 2+|vd |1010111|VADD.VS
2+|00000|vm |vs2 |rs1 |010 2+|vd |1010111|VADD.VX
2+|00000|vm |vs2 |simm[4:0]|011 2+|vd |1010111|VADD.VI
|========================

.Vector Table
[width="100%",cols="^3,^3,^3,^4,^4,^3,^3,^3,^7,<10"]
|========================
Expand Down Expand Up @@ -398,3 +416,4 @@ vx4mulsub
2+|vs3|vm|vs2|vs1|110 2+|vd|1001111|VMSUBW.VVS

|========================
////
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