Add support for Zfh extension (riscv#129)

rmn30 · Jan 19, 2022 · 612958b · 612958b
1 parent 56125e6
commit 612958b
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Showing 21 changed files with 3,067 additions and 13 deletions.
diff --git a/Makefile b/Makefile
@@ -27,6 +27,9 @@ SAIL_DEFAULT_INST += riscv_insts_zba.sail
 SAIL_DEFAULT_INST += riscv_insts_zbb.sail
 SAIL_DEFAULT_INST += riscv_insts_zbc.sail
 SAIL_DEFAULT_INST += riscv_insts_zbs.sail
+
+SAIL_DEFAULT_INST += riscv_insts_zfh.sail
+
 SAIL_DEFAULT_INST += riscv_insts_zkn.sail
 SAIL_DEFAULT_INST += riscv_insts_zks.sail
 

diff --git a/c_emulator/riscv_softfloat.c b/c_emulator/riscv_softfloat.c
@@ -17,6 +17,58 @@ static uint_fast8_t uint8_of_rm(mach_bits rm) {
   zfloat_result = res.v;                                    \
   zfloat_fflags |= (mach_bits) softfloat_exceptionFlags     \
 
+unit softfloat_f16add(mach_bits rm, mach_bits v1, mach_bits v2) {
+  SOFTFLOAT_PRELUDE(rm);
+
+  float16_t a, b, res;
+  a.v = v1;
+  b.v = v2;
+  res = f16_add(a, b);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
+unit softfloat_f16sub(mach_bits rm, mach_bits v1, mach_bits v2) {
+  SOFTFLOAT_PRELUDE(rm);
+
+  float16_t a, b, res;
+  a.v = v1;
+  b.v = v2;
+  res = f16_sub(a, b);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
+unit softfloat_f16mul(mach_bits rm, mach_bits v1, mach_bits v2) {
+  SOFTFLOAT_PRELUDE(rm);
+
+  float16_t a, b, res;
+  a.v = v1;
+  b.v = v2;
+  res = f16_mul(a, b);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
+unit softfloat_f16div(mach_bits rm, mach_bits v1, mach_bits v2) {
+  SOFTFLOAT_PRELUDE(rm);
+
+  float16_t a, b, res;
+  a.v = v1;
+  b.v = v2;
+  res = f16_div(a, b);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
 unit softfloat_f32add(mach_bits rm, mach_bits v1, mach_bits v2) {
   SOFTFLOAT_PRELUDE(rm);
 
@@ -121,6 +173,20 @@ unit softfloat_f64div(mach_bits rm, mach_bits v1, mach_bits v2) {
   return UNIT;
 }
 
+unit softfloat_f16muladd(mach_bits rm, mach_bits v1, mach_bits v2, mach_bits v3) {
+  SOFTFLOAT_PRELUDE(rm);
+
+  float16_t a, b, c, res;
+  a.v = v1;
+  b.v = v2;
+  c.v = v3;
+  res = f16_mulAdd(a, b, c);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
 unit softfloat_f32muladd(mach_bits rm, mach_bits v1, mach_bits v2, mach_bits v3) {
   SOFTFLOAT_PRELUDE(rm);
 
@@ -149,6 +215,18 @@ unit softfloat_f64muladd(mach_bits rm, mach_bits v1, mach_bits v2, mach_bits v3)
   return UNIT;
 }
 
+unit softfloat_f16sqrt(mach_bits rm, mach_bits v) {
+  SOFTFLOAT_PRELUDE(rm);
+
+  float16_t a, res;
+  a.v = v;
+  res = f16_sqrt(a);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
 unit softfloat_f32sqrt(mach_bits rm, mach_bits v) {
   SOFTFLOAT_PRELUDE(rm);
 
@@ -176,6 +254,62 @@ unit softfloat_f64sqrt(mach_bits rm, mach_bits v) {
 // The boolean 'true' argument in the conversion calls below selects
 // 'exact' conversion, which sets the Inexact exception flag if
 // needed.
+unit softfloat_f16toi32(mach_bits rm, mach_bits v) {
+  SOFTFLOAT_PRELUDE(rm);
+
+  float16_t a;
+  float32_t res;
+  uint_fast8_t rm8 = uint8_of_rm(rm);
+  a.v = v;
+  res.v = f16_to_i32(a, rm8, true);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
+unit softfloat_f16toui32(mach_bits rm, mach_bits v) {
+  SOFTFLOAT_PRELUDE(rm);
+
+  float16_t a;
+  float32_t res;
+  uint_fast8_t rm8 = uint8_of_rm(rm);
+  a.v = v;
+  res.v = f16_to_ui32(a, rm8, true);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
+unit softfloat_f16toi64(mach_bits rm, mach_bits v) {
+  SOFTFLOAT_PRELUDE(rm);
+
+  float16_t a;
+  float64_t res;
+  uint_fast8_t rm8 = uint8_of_rm(rm);
+  a.v = v;
+  res.v = f16_to_i64(a, rm8, true);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
+unit softfloat_f16toui64(mach_bits rm, mach_bits v) {
+  SOFTFLOAT_PRELUDE(rm);
+
+  float16_t a;
+  float64_t res;
+  uint_fast8_t rm8 = uint8_of_rm(rm);
+  a.v = v;
+  res.v = f16_to_ui64(a, rm8, true);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
 unit softfloat_f32toi32(mach_bits rm, mach_bits v) {
   SOFTFLOAT_PRELUDE(rm);
 
@@ -284,6 +418,50 @@ unit softfloat_f64toui64(mach_bits rm, mach_bits v) {
   return UNIT;
 }
 
+unit softfloat_i32tof16(mach_bits rm, mach_bits v) {
+  SOFTFLOAT_PRELUDE(rm);
+
+  float16_t res;
+  res = i32_to_f16((int32_t)v);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
+unit softfloat_ui32tof16(mach_bits rm, mach_bits v) {
+  SOFTFLOAT_PRELUDE(rm);
+
+  float16_t res;
+  res = ui32_to_f16((uint32_t)v);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
+unit softfloat_i64tof16(mach_bits rm, mach_bits v) {
+  SOFTFLOAT_PRELUDE(rm);
+
+  float16_t res;
+  res = i64_to_f16(v);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
+unit softfloat_ui64tof16(mach_bits rm, mach_bits v) {
+  SOFTFLOAT_PRELUDE(rm);
+
+  float16_t res;
+  res = ui64_to_f16(v);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
 unit softfloat_i32tof32(mach_bits rm, mach_bits v) {
   SOFTFLOAT_PRELUDE(rm);
 
@@ -372,6 +550,32 @@ unit softfloat_ui64tof64(mach_bits rm, mach_bits v) {
   return UNIT;
 }
 
+unit softfloat_f16tof32(mach_bits rm, mach_bits v) {
+  SOFTFLOAT_PRELUDE(rm);
+
+  float16_t a;
+  float32_t res;
+  a.v = v;
+  res = f16_to_f32(a);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
+unit softfloat_f16tof64(mach_bits rm, mach_bits v) {
+  SOFTFLOAT_PRELUDE(rm);
+
+  float16_t a;
+  float64_t res;
+  a.v = v;
+  res = f16_to_f64(a);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
 unit softfloat_f32tof64(mach_bits rm, mach_bits v) {
   SOFTFLOAT_PRELUDE(rm);
 
@@ -385,6 +589,32 @@ unit softfloat_f32tof64(mach_bits rm, mach_bits v) {
   return UNIT;
 }
 
+unit softfloat_f32tof16(mach_bits rm, mach_bits v) {
+  SOFTFLOAT_PRELUDE(rm);
+
+  float32_t a;
+  float16_t res;
+  a.v = v;
+  res = f32_to_f16(a);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
+unit softfloat_f64tof16(mach_bits rm, mach_bits v) {
+  SOFTFLOAT_PRELUDE(rm);
+
+  float64_t a;
+  float16_t res;
+  a.v = v;
+  res = f64_to_f16(a);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
 unit softfloat_f64tof32(mach_bits rm, mach_bits v) {
   SOFTFLOAT_PRELUDE(rm);
 
@@ -398,6 +628,45 @@ unit softfloat_f64tof32(mach_bits rm, mach_bits v) {
   return UNIT;
 }
 
+unit softfloat_f16lt(mach_bits v1, mach_bits v2) {
+  SOFTFLOAT_PRELUDE(0);
+
+  float16_t a, b, res;
+  a.v = v1;
+  b.v = v2;
+  res.v = f16_lt(a, b);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
+unit softfloat_f16le(mach_bits v1, mach_bits v2) {
+  SOFTFLOAT_PRELUDE(0);
+
+  float16_t a, b, res;
+  a.v = v1;
+  b.v = v2;
+  res.v = f16_le(a, b);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
+unit softfloat_f16eq(mach_bits v1, mach_bits v2) {
+  SOFTFLOAT_PRELUDE(0);
+
+  float16_t a, b, res;
+  a.v = v1;
+  b.v = v2;
+  res.v = f16_eq(a, b);
+
+  SOFTFLOAT_POSTLUDE(res);
+
+  return UNIT;
+}
+
 unit softfloat_f32lt(mach_bits v1, mach_bits v2) {
   SOFTFLOAT_PRELUDE(0);
 

diff --git a/c_emulator/riscv_softfloat.h b/c_emulator/riscv_softfloat.h
@@ -1,5 +1,10 @@
 #pragma once
 
+unit softfloat_f16add(mach_bits rm, mach_bits v1, mach_bits v2);
+unit softfloat_f16sub(mach_bits rm, mach_bits v1, mach_bits v2);
+unit softfloat_f16mul(mach_bits rm, mach_bits v1, mach_bits v2);
+unit softfloat_f16div(mach_bits rm, mach_bits v1, mach_bits v2);
+
 unit softfloat_f32add(mach_bits rm, mach_bits v1, mach_bits v2);
 unit softfloat_f32sub(mach_bits rm, mach_bits v1, mach_bits v2);
 unit softfloat_f32mul(mach_bits rm, mach_bits v1, mach_bits v2);
@@ -10,12 +15,19 @@ unit softfloat_f64sub(mach_bits rm, mach_bits v1, mach_bits v2);
 unit softfloat_f64mul(mach_bits rm, mach_bits v1, mach_bits v2);
 unit softfloat_f64div(mach_bits rm, mach_bits v1, mach_bits v2);
 
+unit softfloat_f16muladd(mach_bits rm, mach_bits v1, mach_bits v2, mach_bits v3);
 unit softfloat_f32muladd(mach_bits rm, mach_bits v1, mach_bits v2, mach_bits v3);
 unit softfloat_f64muladd(mach_bits rm, mach_bits v1, mach_bits v2, mach_bits v3);
 
+unit softfloat_f16sqrt(mach_bits rm, mach_bits v);
 unit softfloat_f32sqrt(mach_bits rm, mach_bits v);
 unit softfloat_f64sqrt(mach_bits rm, mach_bits v);
 
+unit softfloat_f16toi32(mach_bits rm, mach_bits v);
+unit softfloat_f16toui32(mach_bits rm, mach_bits v);
+unit softfloat_f16toi64(mach_bits rm, mach_bits v);
+unit softfloat_f16toui64(mach_bits rm, mach_bits v);
+
 unit softfloat_f32toi32(mach_bits rm, mach_bits v);
 unit softfloat_f32toui32(mach_bits rm, mach_bits v);
 unit softfloat_f32toi64(mach_bits rm, mach_bits v);
@@ -26,6 +38,11 @@ unit softfloat_f64toui32(mach_bits rm, mach_bits v);
 unit softfloat_f64toi64(mach_bits rm, mach_bits v);
 unit softfloat_f64toui64(mach_bits rm, mach_bits v);
 
+unit softfloat_i32tof16(mach_bits rm, mach_bits v);
+unit softfloat_ui32tof16(mach_bits rm, mach_bits v);
+unit softfloat_i64tof16(mach_bits rm, mach_bits v);
+unit softfloat_ui64tof16(mach_bits rm, mach_bits v);
+
 unit softfloat_i32tof32(mach_bits rm, mach_bits v);
 unit softfloat_ui32tof32(mach_bits rm, mach_bits v);
 unit softfloat_i64tof32(mach_bits rm, mach_bits v);
@@ -36,9 +53,17 @@ unit softfloat_ui32tof64(mach_bits rm, mach_bits v);
 unit softfloat_i64tof64(mach_bits rm, mach_bits v);
 unit softfloat_ui64tof64(mach_bits rm, mach_bits v);
 
+unit softfloat_f16tof32(mach_bits rm, mach_bits v);
+unit softfloat_f16tof64(mach_bits rm, mach_bits v);
 unit softfloat_f32tof64(mach_bits rm, mach_bits v);
+
+unit softfloat_f32tof16(mach_bits rm, mach_bits v);
+unit softfloat_f64tof16(mach_bits rm, mach_bits v);
 unit softfloat_f64tof32(mach_bits rm, mach_bits v);
 
+unit softfloat_f16lt(mach_bits v1, mach_bits v2);
+unit softfloat_f16le(mach_bits v1, mach_bits v2);
+unit softfloat_f16eq(mach_bits v1, mach_bits v2);
 unit softfloat_f32lt(mach_bits v1, mach_bits v2);
 unit softfloat_f32le(mach_bits v1, mach_bits v2);
 unit softfloat_f32eq(mach_bits v1, mach_bits v2);