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Rollup merge of #136356 - pthariensflame:patch-1, r=tgross35
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Docs for f16 and f128: correct a typo and add details

CC: #116909; corrects and expands #124750.
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jieyouxu authored Feb 3, 2025
2 parents 7daf4cf + baa1cdd commit 7be7f3b
Showing 1 changed file with 7 additions and 7 deletions.
14 changes: 7 additions & 7 deletions library/core/src/primitive_docs.rs
Original file line number Diff line number Diff line change
Expand Up @@ -1160,9 +1160,9 @@ impl<T> (T,) {}
///
/// Note that most common platforms will not support `f16` in hardware without enabling extra target
/// features, with the notable exception of Apple Silicon (also known as M1, M2, etc.) processors.
/// Hardware support on x86-64 requires the avx512fp16 feature, while RISC-V requires Zhf.
/// Usually the fallback implementation will be to use `f32` hardware if it exists, and convert
/// between `f16` and `f32` when performing math.
/// Hardware support on x86/x86-64 requires the avx512fp16 or avx10.1 features, while RISC-V requires
/// Zfh, and Arm/AArch64 requires FEAT_FP16. Usually the fallback implementation will be to use `f32`
/// hardware if it exists, and convert between `f16` and `f32` when performing math.
///
/// *[See also the `std::f16::consts` module](crate::f16::consts).*
///
Expand Down Expand Up @@ -1344,10 +1344,10 @@ mod prim_f64 {}
/// quad-precision values][wikipedia] for more information.
///
/// Note that no platforms have hardware support for `f128` without enabling target specific features,
/// as for all instruction set architectures `f128` is considered an optional feature.
/// Only Power ISA ("PowerPC") and RISC-V specify it, and only certain microarchitectures
/// actually implement it. For x86-64 and AArch64, ISA support is not even specified,
/// so it will always be a software implementation significantly slower than `f64`.
/// as for all instruction set architectures `f128` is considered an optional feature. Only Power ISA
/// ("PowerPC") and RISC-V (via the Q extension) specify it, and only certain microarchitectures
/// actually implement it. For x86-64 and AArch64, ISA support is not even specified, so it will always
/// be a software implementation significantly slower than `f64`.
///
/// _Note: `f128` support is incomplete. Many platforms will not be able to link math functions. On
/// x86 in particular, these functions do link but their results are always incorrect._
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