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targets: thumbv8m: Add target for baseline ARMv8-M #55041

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Dec 4, 2018
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1 change: 1 addition & 0 deletions src/librustc_target/spec/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -397,6 +397,7 @@ supported_targets! {
("thumbv7m-none-eabi", thumbv7m_none_eabi),
("thumbv7em-none-eabi", thumbv7em_none_eabi),
("thumbv7em-none-eabihf", thumbv7em_none_eabihf),
("thumbv8m-none-eabi", thumbv8m_none_eabi),
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thumbv8m.base-none-eabi would be better to distinguish from a thumbv8m.main target in the future.


("msp430-none-elf", msp430_none_elf),

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5 changes: 3 additions & 2 deletions src/librustc_target/spec/thumb_base.rs
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
// option. This file may not be copied, modified, or distributed
// except according to those terms.

// These 4 `thumbv*` targets cover the ARM Cortex-M family of processors which are widely used in
// These `thumbv*` targets cover the ARM Cortex-M family of processors which are widely used in
// microcontrollers. Namely, all these processors:
//
// - Cortex-M0
Expand All @@ -17,8 +17,9 @@
// - Cortex-M3
// - Cortex-M4(F)
// - Cortex-M7(F)
// - Cortex-M23
//
// We have opted for 4 targets instead of one target per processor (e.g. `cortex-m0`, `cortex-m3`,
// We have opted for these instead of one target per processor (e.g. `cortex-m0`, `cortex-m3`,
// etc) because the differences between some processors like the cortex-m0 and cortex-m1 are almost
// non-existent from the POV of codegen so it doesn't make sense to have separate targets for them.
// And if differences exist between two processors under the same target, rustc flags can be used to
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33 changes: 33 additions & 0 deletions src/librustc_target/spec/thumbv8m_none_eabi.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,33 @@
// Copyright 2018 The Rust Project Developers. See the COPYRIGHT
// file at the top-level directory of this distribution and at
// http://rust-lang.org/COPYRIGHT.
//
// Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
// http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
// <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
// option. This file may not be copied, modified, or distributed
// except according to those terms.

// Targets the Cortex-M23 processor (Baseline ARMv8-M)

use spec::{LinkerFlavor, LldFlavor, Target, TargetOptions, TargetResult};

pub fn target() -> TargetResult {
Ok(Target {
llvm_target: "thumbv8m.base-none-eabi".to_string(),
target_endian: "little".to_string(),
target_pointer_width: "32".to_string(),
target_c_int_width: "32".to_string(),
data_layout: "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64".to_string(),
arch: "arm".to_string(),
target_os: "none".to_string(),
target_env: String::new(),
target_vendor: String::new(),
linker_flavor: LinkerFlavor::Lld(LldFlavor::Ld),

options: TargetOptions {
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The baseline architecture doesn't support unaligned access, so features: "+strict-align".to_string(), will need to be added here as I believe it's not enabled by default.

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So, it looks like the "Main Extension" from 8-M was a baseline in 7-M? And this newly added target (used for Cortex-M23) is not really a baseline but mainline?

Any other notable changes in 8-M affecting codegen? The "changelog" in ARM ARM doesn't tell much to me.

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Aha! Good catch @parched, I will adjust.

I took a look at this description of changes here: https://community.arm.com/processors/trustzone-for-armv8-m/b/blog/posts/five-key-features-of-the-arm-cortex-m23-processor?CommentId=f95326ae-7e58-4829-9874-a1ebd4a141e9

I think I may have atomic instruction support incorrectly configured. Per the above blog post:

In addition, to provide atomic support for C11/C++11, the load-acquire and store-release instructions are included from ARMv8-A

There is no mention of atomic CAS support, I think that I may need to set atomic_cas: false while keeping max_atomic_width: Some(32),. https://reviews.llvm.org/D15283?id=42050 also seems to hint at this. Does this seem correct?

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I think I may have atomic instruction support incorrectly configured.

No, you have it correct already :).

ARMv8-M Baseline is a superset of ARMv6-M, containing all ARMv6-M instructions plus ARMv8-A semaphores and atomics, ARMv7-M exclusives

This is what gives it CAS support.

max_atomic_width: Some(32),
.. super::thumb_base::opts()
},
})
}