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[LLVM] [RVV 0.7.1] Implement RVV 0.7.1 indexed load/store intrinsics. (
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…#28)

* [LLVM] [RVV 0.7.1] Define intrinsics for indexed
load.

* [LLVM] [RVV 0.7.1] Define pseudo nodes for indexed
load.

* [LLVM] [RVV 0.7.1] Expand pseudo indexed load
nodes.

* [LLVM] [RVV 0.7.1] Set RVV load info for newly
added intrinsics.

* [LLVM] [RVV 0.7.1] Add test cases for indexed load
intrinsics.

* [LLVM] [RVV 0.7.1] Define intrinsics for indexed
store.

* [LLVM] [RVV 0.7.1] Define pseudo nodes for indexed
store intrinsic.

* [LLVM] [RVV 0.7.1] Expand pseudo indexed store
nodes.

* [LLVM] [RVV 0.7.1] Set RVV store info for indexed
store.

* [LLVM] [RVV 0.7.1] Add tests for indexed store.
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AinsleySnow authored Nov 27, 2023
1 parent 7baa7b2 commit 52fd62a
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Showing 11 changed files with 7,136 additions and 48 deletions.
64 changes: 64 additions & 0 deletions llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td
Original file line number Diff line number Diff line change
Expand Up @@ -172,6 +172,70 @@ let TargetPrefix = "riscv" in {
def int_riscv_xvssh_mask : XVSStoreMasked;
def int_riscv_xvssw_mask : XVSStoreMasked;
def int_riscv_xvsse_mask : XVSStoreMasked;

// 7.6. Vector Indexed Instructions
// For indexed load with passthru operand
// Input: (passthru, pointer, index, vl)
class XVILoad
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_ptr_ty,
llvm_anyvector_ty, llvm_anyint_ty],
[NoCapture<ArgIndex<1>>, IntrReadMem]>, RISCVVIntrinsic {
let VLOperand = 3;
}
// For indexed load with mask
// Input: (maskedoff, pointer, index, mask, vl)
class XVILoadMasked
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_ptr_ty, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
[NoCapture<ArgIndex<1>>, IntrReadMem]>,
RISCVVIntrinsic {
let VLOperand = 4;
}

// For indexed store
// Input: (vector_in, pointer, index, vl)
class XVIStore
: DefaultAttrsIntrinsic<[],
[llvm_anyvector_ty, llvm_ptr_ty,
llvm_anyvector_ty, llvm_anyint_ty],
[NoCapture<ArgIndex<1>>, IntrWriteMem]>, RISCVVIntrinsic {
let VLOperand = 3;
}
// For indexed store with mask
// Input: (vector_in, pointer, index, mask, vl)
class XVIStoreMasked
: DefaultAttrsIntrinsic<[],
[llvm_anyvector_ty, llvm_ptr_ty, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
[NoCapture<ArgIndex<1>>, IntrWriteMem]>, RISCVVIntrinsic {
let VLOperand = 4;
}

def int_riscv_xvlxb : XVILoad;
def int_riscv_xvlxh : XVILoad;
def int_riscv_xvlxw : XVILoad;
def int_riscv_xvlxe : XVILoad;
def int_riscv_xvlxbu : XVILoad;
def int_riscv_xvlxhu : XVILoad;
def int_riscv_xvlxwu : XVILoad;
def int_riscv_xvlxb_mask : XVILoadMasked;
def int_riscv_xvlxh_mask : XVILoadMasked;
def int_riscv_xvlxw_mask : XVILoadMasked;
def int_riscv_xvlxe_mask : XVILoadMasked;
def int_riscv_xvlxbu_mask : XVILoadMasked;
def int_riscv_xvlxhu_mask : XVILoadMasked;
def int_riscv_xvlxwu_mask : XVILoadMasked;

def int_riscv_xvsxb : XVIStore;
def int_riscv_xvsxh : XVIStore;
def int_riscv_xvsxw : XVIStore;
def int_riscv_xvsxe : XVIStore;
def int_riscv_xvsxb_mask : XVIStoreMasked;
def int_riscv_xvsxh_mask : XVIStoreMasked;
def int_riscv_xvsxw_mask : XVIStoreMasked;
def int_riscv_xvsxe_mask : XVIStoreMasked;
} // TargetPrefix = "riscv"

let TargetPrefix = "riscv" in {
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