Initial commit, running Debain successfully building with Vivado 2017.1

s117 · Jul 21, 2017 · 8144cff · 8144cff
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diff --git a/piton/design/chip/chip_bridge/xilinx/zc706/ip_cores/afifo_w3_d16/afifo_w3_d16.xci b/piton/design/chip/chip_bridge/xilinx/zc706/ip_cores/afifo_w3_d16/afifo_w3_d16.xci
diff --git a/piton/design/chip/chip_bridge/xilinx/zc706/ip_cores/afifo_w3_d16/afifo_w3_d16.xml b/piton/design/chip/chip_bridge/xilinx/zc706/ip_cores/afifo_w3_d16/afifo_w3_d16.xml
diff --git a/piton/design/chip/chip_bridge/xilinx/zc706/ip_cores/afifo_w64_d16/afifo_w64_d16.xci b/piton/design/chip/chip_bridge/xilinx/zc706/ip_cores/afifo_w64_d16/afifo_w64_d16.xci
diff --git a/piton/design/chip/chip_bridge/xilinx/zc706/ip_cores/afifo_w64_d16/afifo_w64_d16.xml b/piton/design/chip/chip_bridge/xilinx/zc706/ip_cores/afifo_w64_d16/afifo_w64_d16.xml
diff --git a/piton/design/chip/chip_bridge/xilinx/zc706/ip_cores/fifo_w3_d16/fifo_w3_d16.xci b/piton/design/chip/chip_bridge/xilinx/zc706/ip_cores/fifo_w3_d16/fifo_w3_d16.xci
diff --git a/piton/design/chip/chip_bridge/xilinx/zc706/ip_cores/fifo_w3_d16/fifo_w3_d16.xml b/piton/design/chip/chip_bridge/xilinx/zc706/ip_cores/fifo_w3_d16/fifo_w3_d16.xml
diff --git a/piton/design/chip/chip_bridge/xilinx/zc706/ip_cores/fifo_w64_d16/fifo_w64_d16.xci b/piton/design/chip/chip_bridge/xilinx/zc706/ip_cores/fifo_w64_d16/fifo_w64_d16.xci
diff --git a/piton/design/chip/chip_bridge/xilinx/zc706/ip_cores/fifo_w64_d16/fifo_w64_d16.xml b/piton/design/chip/chip_bridge/xilinx/zc706/ip_cores/fifo_w64_d16/fifo_w64_d16.xml
diff --git a/piton/design/chip/tile/l15/xilinx/zc706/ip_cores/bram_512x128/bram_512x128.xci b/piton/design/chip/tile/l15/xilinx/zc706/ip_cores/bram_512x128/bram_512x128.xci
diff --git a/piton/design/chip/tile/l15/xilinx/zc706/ip_cores/bram_512x128/bram_512x128.xml b/piton/design/chip/tile/l15/xilinx/zc706/ip_cores/bram_512x128/bram_512x128.xml
diff --git a/piton/design/chip/tile/l15/xilinx/zc706/ip_cores/bram_512x32/bram_512x32.xci b/piton/design/chip/tile/l15/xilinx/zc706/ip_cores/bram_512x32/bram_512x32.xci
diff --git a/piton/design/chip/tile/l15/xilinx/zc706/ip_cores/bram_512x32/bram_512x32.xml b/piton/design/chip/tile/l15/xilinx/zc706/ip_cores/bram_512x32/bram_512x32.xml
diff --git a/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_1024x64/bram_1024x64.xci b/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_1024x64/bram_1024x64.xci
diff --git a/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_1024x64/bram_1024x64.xml b/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_1024x64/bram_1024x64.xml
diff --git a/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_2048x144/bram_2048x144.xci b/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_2048x144/bram_2048x144.xci
diff --git a/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_2048x144/bram_2048x144.xml b/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_2048x144/bram_2048x144.xml
diff --git a/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_256x104/bram_256x104.xci b/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_256x104/bram_256x104.xci
diff --git a/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_256x104/bram_256x104.xml b/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_256x104/bram_256x104.xml
diff --git a/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_2p_128x176/bram_2p_128x176.xci b/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_2p_128x176/bram_2p_128x176.xci
diff --git a/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_2p_128x176/bram_2p_128x176.xml b/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_2p_128x176/bram_2p_128x176.xml
diff --git a/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_2p_256x176/bram_2p_256x176.xci b/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_2p_256x176/bram_2p_256x176.xci
diff --git a/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_2p_256x176/bram_2p_256x176.xml b/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_2p_256x176/bram_2p_256x176.xml
diff --git a/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_4096x144/bram_4096x144.xci b/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_4096x144/bram_4096x144.xci
diff --git a/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_4096x144/bram_4096x144.xml b/piton/design/chip/tile/l2/xilinx/zc706/ip_cores/bram_4096x144/bram_4096x144.xml
diff --git a/piton/design/chip/tile/sparc/srams/xilinx/zc706/ip_cores/bram_128x132/bram_128x132.xci b/piton/design/chip/tile/sparc/srams/xilinx/zc706/ip_cores/bram_128x132/bram_128x132.xci
diff --git a/piton/design/chip/tile/sparc/srams/xilinx/zc706/ip_cores/bram_128x132/bram_128x132.xml b/piton/design/chip/tile/sparc/srams/xilinx/zc706/ip_cores/bram_128x132/bram_128x132.xml
diff --git a/piton/design/chip/tile/sparc/srams/xilinx/zc706/ip_cores/bram_128x576/bram_128x576.xci b/piton/design/chip/tile/sparc/srams/xilinx/zc706/ip_cores/bram_128x576/bram_128x576.xci
diff --git a/piton/design/chip/tile/sparc/srams/xilinx/zc706/ip_cores/bram_128x576/bram_128x576.xml b/piton/design/chip/tile/sparc/srams/xilinx/zc706/ip_cores/bram_128x576/bram_128x576.xml
diff --git a/piton/design/chip/tile/sparc/srams/xilinx/zc706/ip_cores/bram_128x78/bram_128x78.xci b/piton/design/chip/tile/sparc/srams/xilinx/zc706/ip_cores/bram_128x78/bram_128x78.xci
diff --git a/piton/design/chip/tile/sparc/srams/xilinx/zc706/ip_cores/bram_128x78/bram_128x78.xml b/piton/design/chip/tile/sparc/srams/xilinx/zc706/ip_cores/bram_128x78/bram_128x78.xml
diff --git a/piton/design/chip/tile/sparc/srams/xilinx/zc706/ip_cores/bram_256x272/bram_256x272.xci b/piton/design/chip/tile/sparc/srams/xilinx/zc706/ip_cores/bram_256x272/bram_256x272.xci
diff --git a/piton/design/chip/tile/sparc/srams/xilinx/zc706/ip_cores/bram_256x272/bram_256x272.xml b/piton/design/chip/tile/sparc/srams/xilinx/zc706/ip_cores/bram_256x272/bram_256x272.xml
diff --git a/piton/design/chip/xilinx/zc706/ip_cores/clk_mmcm_chip/clk_mmcm_chip.xci b/piton/design/chip/xilinx/zc706/ip_cores/clk_mmcm_chip/clk_mmcm_chip.xci
diff --git a/piton/design/chip/xilinx/zc706/ip_cores/clk_mmcm_chip/clk_mmcm_chip.xml b/piton/design/chip/xilinx/zc706/ip_cores/clk_mmcm_chip/clk_mmcm_chip.xml
diff --git a/piton/design/chipset/include/chipset_define.vh b/piton/design/chipset/include/chipset_define.vh
@@ -1,7 +1,7 @@
 // ========== Copyright Header Begin ============================================
 // Copyright (c) 2015 Princeton University
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are met:
 //     * Redistributions of source code must retain the above copyright
@@ -12,7 +12,7 @@
 //     * Neither the name of Princeton University nor the
 //       names of its contributors may be used to endorse or promote products
 //       derived from this software without specific prior written permission.
-// 
+//
 // THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND
 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -84,6 +84,9 @@
 `elsif GENESYS2_BOARD       // 32-bit PHY
     `define ADDR_TRANS_PHYS_WIDTH_ALIGN     5
     `define ADDR_TRANS_SECTION_MULT         2
+`elsif ZC706_BOARD         // 64-bit PHY
+    `define ADDR_TRANS_PHYS_WIDTH_ALIGN     6
+    `define ADDR_TRANS_SECTION_MULT         1
 `else   // 64-bit interface by default
     `define ADDR_TRANS_PHYS_WIDTH_ALIGN     6
     `define ADDR_TRANS_SECTION_MULT         1

diff --git a/piton/design/chipset/include/mc_define.h b/piton/design/chipset/include/mc_define.h
@@ -1,7 +1,7 @@
 // ========== Copyright Header Begin ============================================
 // Copyright (c) 2015 Princeton University
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are met:
 //     * Redistributions of source code must retain the above copyright
@@ -12,7 +12,7 @@
 //     * Neither the name of Princeton University nor the
 //       names of its contributors may be used to endorse or promote products
 //       derived from this software without specific prior written permission.
-// 
+//
 // THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND
 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -47,7 +47,7 @@
     `define MIG_APP_ADDR_WIDTH      27
     `define MIG_APP_CMD_WIDTH       3
     `define MIG_APP_DATA_WIDTH      128
-    `define MIG_APP_BURST_OFFSET    4   // in bits: logb2(MIG_APP_DATA_WIDTH / 8) 
+    `define MIG_APP_BURST_OFFSET    4   // in bits: logb2(MIG_APP_DATA_WIDTH / 8)
     `define MIG_APP_MASK_WIDTH      16
 
     `define DDR3_DQ_WIDTH           16
@@ -73,11 +73,26 @@
     `define DDR3_CK_WIDTH           1
     `define DDR3_CKE_WIDTH          1
     `define DDR3_CS_WIDTH           1
+`elsif ZC706_BOARD
+    `define MIG_APP_ADDR_WIDTH      28
+    `define MIG_APP_CMD_WIDTH       3
+    `define MIG_APP_DATA_WIDTH      512
+    `define MIG_APP_BURST_OFFSET    6      // in bits: logb2(MIG_APP_DATA_WIDTH / 8)
+    `define MIG_APP_MASK_WIDTH      64
+
+    `define DDR3_DQ_WIDTH           64
+    `define DDR3_DQS_WIDTH          8
+    `define DDR3_ADDR_WIDTH         14
+    `define DDR3_BA_WIDTH           3
+    `define DDR3_DM_WIDTH           8
+    `define DDR3_CK_WIDTH           1
+    `define DDR3_CKE_WIDTH          1
+    `define DDR3_CS_WIDTH           1
 `elsif NEXYSVIDEO_BOARD
     `define MIG_APP_ADDR_WIDTH      29
     `define MIG_APP_CMD_WIDTH       3
     `define MIG_APP_DATA_WIDTH      128
-    `define MIG_APP_BURST_OFFSET    4   // in bits: logb2(MIG_APP_DATA_WIDTH / 8) 
+    `define MIG_APP_BURST_OFFSET    4   // in bits: logb2(MIG_APP_DATA_WIDTH / 8)
     `define MIG_APP_MASK_WIDTH      16
 
     `define DDR3_DQ_WIDTH           16

diff --git a/piton/design/chipset/io_ctrl/xilinx/zc706/ip_cores/atg_uart_init/atg_uart_init.xci b/piton/design/chipset/io_ctrl/xilinx/zc706/ip_cores/atg_uart_init/atg_uart_init.xci