SOC-Design

Section 1

1. Run 'picorv32a'synthesis:

2. Calculate the Flop Ratio

Flop Ratio= 1213/14876= 0.108429685 Percentage of DFF's= 0.108429685*100= 10.84296854

Section 2: Floorplan and Library Cells

1. Run Floorplan

2. Calculate Die Area

1000 Unit Distance= 1 Micron
Die within Unit Distance = 660685 − 0 = 660685
Die height in unit Distance = 671405 − 0 = 671405
Distance in Microns=Value in Unit Distance 1000
Die width in Microns = 660685 1000 = 660.685 MIcrons Die Height in Microns = 671405 1000 = 671.405 Microns
Area of Die in Microns = 660.685 ∗ 671.405 = 443587.212425Square Microns

3. Load Generated floorplan in Magic

4.Run congestion aware placement

5. Load denerated placement def in Magic and explore the placement

Section 3

1.Clone custom inverter cell

2.Load the layout in Magic and explore

3. SPICE extraction of inverter in Magic

4. Editing the SPICE model file for analysis through simulation

5. Post-Layout ngspice simulations

6. Find problem in DRC section of magic file

Section 4-Pre-layout timing analysis and imposrtanceof good clock tree

1.Fix up small DRC errors

2.Save the finalized layout and open it

3.Edit config.tcl

5. Remove and reduce newly introduced violations

6.Once Synthesis is over run floorplan

7.Make timing ECO fixes to remove all violations

9.Post-CTS

10.Post-CTS after removing a cell

Section 5

1.Perform deneration of PDN and explore the layout

2. Detailed Routing with TritonRoute and explore

3.Post route parasitic extractiion using SPEF extractor

4.Post-Route openSTA STA