fix: replace pillow with PIL in PACKAGE_LIST

[zhyncs]

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Motivation

python3 -m sglang.check_env

Python: 3.11.5 (main, Sep 11 2023, 13:54:46) [GCC 11.2.0]
CUDA available: True
GPU 0: NVIDIA A100-SXM4-80GB
CUDA_HOME: /usr/local/cuda
NVCC: Cuda compilation tools, release 12.2, V12.2.140
CUDA Driver Version: 535.54.03
PyTorch: 2.3.1+cu121
sglang: 0.2.6
flashinfer: 0.1.1+cu121torch2.3
requests: 2.32.3
tqdm: 4.66.4
numpy: 1.26.4
aiohttp: 3.9.5
fastapi: 0.111.0
hf_transfer: 0.1.6
huggingface_hub: 0.23.4
interegular: 0.3.3
packaging: 24.1
PIL: 10.4.0
psutil: 6.0.0
pydantic: 2.8.2
uvicorn: 0.30.1
uvloop: 0.19.0
zmq: 26.0.3
vllm: 0.5.3.post1
openai: 1.35.13
anthropic: 0.31.1
NVIDIA Topology:
	GPU0	NIC0	NIC1	NIC2	NIC3	NIC4	CPU Affinity	NUMA Affinity	GPU NUMA ID
GPU0	 X 	NODE	NODE	PXB	SYS	SYS	0-31,64-95	0		N/A
NIC0	NODE	 X 	NODE	NODE	SYS	SYS
NIC1	NODE	NODE	 X 	NODE	SYS	SYS
NIC2	PXB	NODE	NODE	 X 	SYS	SYS
NIC3	SYS	SYS	SYS	SYS	 X 	NODE
NIC4	SYS	SYS	SYS	SYS	NODE	 X

Legend:

  X    = Self
  SYS  = Connection traversing PCIe as well as the SMP interconnect between NUMA nodes (e.g., QPI/UPI)
  NODE = Connection traversing PCIe as well as the interconnect between PCIe Host Bridges within a NUMA node
  PHB  = Connection traversing PCIe as well as a PCIe Host Bridge (typically the CPU)
  PXB  = Connection traversing multiple PCIe bridges (without traversing the PCIe Host Bridge)
  PIX  = Connection traversing at most a single PCIe bridge
  NV#  = Connection traversing a bonded set of # NVLinks

NIC Legend:

  NIC0: mlx5_bond_0
  NIC1: mlx5_bond_1
  NIC2: mlx5_bond_2
  NIC3: mlx5_bond_3
  NIC4: mlx5_bond_4


ulimit soft: 1024

Modification

Briefly describe the changes made in this PR.

Checklist

1. Ensure pre-commit pre-commit run --all-files or other linting tools are used to fix potential lint issues.
2. Confirm that modifications are covered by complete unit tests. If not, please add more unit tests for correctness.
3. Modify documentation as needed, such as docstrings or example tutorials.