Fixed Intrinsic.RegisterAssign.prettyST.

sireum · Mar 6, 2025 · 750dc53 · 750dc53
1 parent d4e0ce0
commit 750dc53
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/shared/src/main/scala/org/sireum/anvil/Intrinsic.scala b/shared/src/main/scala/org/sireum/anvil/Intrinsic.scala
@@ -99,7 +99,7 @@ object Intrinsic {
       val reg: String = if (isSP) "SP" else "DP"
       value match {
         case AST.IR.Exp.Int(_, v, _) => if (isInc) if (v < 0) st"$reg = $reg - ${-v}" else st"$reg = $reg + $v" else st"$reg = $v"
-        case _ => st"$reg = $reg + ${value.prettyST}"
+        case _ => if (isInc) st"$reg = $reg + ${value.prettyST}" else st"$reg = ${value.prettyST}"
       }
     }
   }