adding more RST_ASYNC_G support

axi/axi-lite/rtl/AxiDualPortRam.vhd

@@ -25,6 +25,7 @@ use surf.AxiLitePkg.all;
 entity AxiDualPortRam is
    generic (
       TPD_G               : time                       := 1 ns;
+      RST_ASYNC_G         : boolean                    := false;
       SYNTH_MODE_G        : string                     := "inferred";
       MEMORY_TYPE_G       : string                     := "block";
       MEMORY_INIT_FILE_G  : string                     := "none";  -- Used for MEMORY_TYPE_G="XPM only
@@ -201,6 +202,7 @@ begin
          DualPortRam_1 : entity surf.DualPortRam
             generic map (
                TPD_G         => TPD_G,
+               RST_ASYNC_G   => RST_ASYNC_G,
                MEMORY_TYPE_G => MEMORY_TYPE_G,
                REG_EN_G      => ite(READ_LATENCY_G >= 1, true, false),
                DOA_REG_G     => ite(READ_LATENCY_G >= 2, true, false),
@@ -232,6 +234,7 @@ begin
          DualPortRam_1 : entity surf.DualPortRam
             generic map (
                TPD_G         => TPD_G,
+               RST_ASYNC_G   => RST_ASYNC_G,
                MEMORY_TYPE_G => MEMORY_TYPE_G,
                REG_EN_G      => ite(READ_LATENCY_G >= 1, true, false),
                DOA_REG_G     => ite(READ_LATENCY_G >= 2, true, false),
@@ -261,6 +264,7 @@ begin
          U_TrueDualPortRam_1 : entity surf.TrueDualPortRam
             generic map (
                TPD_G        => TPD_G,
+               RST_ASYNC_G  => RST_ASYNC_G,
                BYTE_WR_EN_G => true,
                DOA_REG_G    => ite(READ_LATENCY_G >= 2, true, false),
                DOB_REG_G    => ite(READ_LATENCY_G >= 2, true, false),
@@ -301,6 +305,7 @@ begin
    U_SynchronizerFifo_1 : entity surf.SynchronizerFifo
       generic map (
          TPD_G         => TPD_G,
+         RST_ASYNC_G   => RST_ASYNC_G,
          COMMON_CLK_G  => COMMON_CLK_G,
          MEMORY_TYPE_G => "distributed",
          DATA_WIDTH_G  => ADDR_WIDTH_G+DATA_WIDTH_G+ADDR_AXI_BYTES_C)
@@ -387,7 +392,7 @@ begin
       end case;
 
       -- Reset
-      if (axiRst = '1') then
+      if (RST_ASYNC_G = false and axiRst = '1') then
          v := REG_INIT_C;
       end if;
 
@@ -400,18 +405,22 @@ begin
 
    end process comb;
 
-   seq : process (axiClk) is
+   seq : process (axiClk, axiRst) is
    begin
-      if (rising_edge(axiClk)) then
+      if (RST_ASYNC_G and axiRst = '1') then
+         r <= REG_INIT_C after TPD_G;
+      elsif rising_edge(axiClk) then
          r <= rin after TPD_G;
       end if;
    end process seq;
 
    OUT_REG : if((READ_LATENCY_G = 3) and (SYNTH_MODE_G /= "xpm")) generate
-      REG : process (clk) is
+      REG : process (clk, rst) is
       begin
-         if(rising_edge(clk)) then
-            if (rst = '1') then
+         if (RST_ASYNC_G and rst = '1') then
+            dout <= (others => '0');
+         elsif (rising_edge(clk)) then
+            if (RST_ASYNC_G = false and rst = '1') then
                dout <= (others => '0');
             else
                dout <= doutInt;

axi/axi-lite/rtl/AxiLiteAsync.vhd

@@ -19,18 +19,18 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiLitePkg.all;
 
 entity AxiLiteAsync is
    generic (
       TPD_G            : time                  := 1 ns;
+      RST_ASYNC_G      : boolean               := false;
       AXI_ERROR_RESP_G : slv(1 downto 0)       := AXI_RESP_SLVERR_C;
-      COMMON_CLK_G    : boolean               := false;
-      NUM_ADDR_BITS_G : natural               := 32;
-      PIPE_STAGES_G   : integer range 0 to 16 := 0);
+      COMMON_CLK_G     : boolean               := false;
+      NUM_ADDR_BITS_G  : natural               := 32;
+      PIPE_STAGES_G    : integer range 0 to 16 := 0);
    port (
       -- Slave Port
       sAxiClk         : in  sl;
@@ -120,8 +120,6 @@ begin
          asyncRst => mAxiClkRst,
          syncRst  => m2sRst);
 
-
-
    ------------------------------------
    -- Read: Slave to Master
    ------------------------------------
@@ -130,6 +128,7 @@ begin
    U_ReadSlaveToMastFifo : entity surf.FifoASync
       generic map (
          TPD_G          => TPD_G,
+         RST_ASYNC_G    => RST_ASYNC_G,
          RST_POLARITY_G => '1',
          MEMORY_TYPE_G  => "distributed", -- Use Dist Ram
          FWFT_EN_G      => true,
@@ -184,7 +183,6 @@ begin
    mAxiReadMaster.arvalid <= readSlaveToMastValid;
    readSlaveToMastRead    <= mAxiReadSlave.arready;
 
-
    ------------------------------------
    -- Read: Master To Slave
    ------------------------------------
@@ -193,6 +191,7 @@ begin
    U_ReadMastToSlaveFifo : entity surf.FifoASync
       generic map (
          TPD_G          => TPD_G,
+         RST_ASYNC_G    => RST_ASYNC_G,
          RST_POLARITY_G => '1',
          MEMORY_TYPE_G  => "distributed", -- Use Dist Ram
          FWFT_EN_G      => true,
@@ -242,7 +241,6 @@ begin
    sAxiReadSlave.rvalid <= ite(m2sRst = '0', readMastToSlaveValid, '1');
    readMastToSlaveRead  <= sAxiReadMaster.rready;
 
-
    ------------------------------------
    -- Write Addr : Slave To Master
    ------------------------------------
@@ -251,6 +249,7 @@ begin
    U_WriteAddrSlaveToMastFifo : entity surf.FifoASync
       generic map (
          TPD_G          => TPD_G,
+         RST_ASYNC_G    => RST_ASYNC_G,
          RST_POLARITY_G => '1',
          MEMORY_TYPE_G  => "distributed", -- Use Dist Ram
          FWFT_EN_G      => true,
@@ -305,7 +304,6 @@ begin
    mAxiWriteMaster.awvalid  <= writeAddrSlaveToMastValid;
    writeAddrSlaveToMastRead <= mAxiWriteSlave.awready;
 
-
    ------------------------------------
    -- Write Data : Slave to Master
    ------------------------------------
@@ -314,6 +312,7 @@ begin
    U_WriteDataSlaveToMastFifo : entity surf.FifoASync
       generic map (
          TPD_G          => TPD_G,
+         RST_ASYNC_G    => RST_ASYNC_G,
          RST_POLARITY_G => '1',
          MEMORY_TYPE_G  => "distributed", -- Use Dist Ram
          FWFT_EN_G      => true,
@@ -363,7 +362,6 @@ begin
    mAxiWriteMaster.wvalid   <= writeDataSlaveToMastValid;
    writeDataSlaveToMastRead <= mAxiWriteSlave.wready;
 
-
    ------------------------------------
    -- Write: Status Master To Slave
    ------------------------------------
@@ -372,6 +370,7 @@ begin
    U_WriteMastToSlaveFifo : entity surf.FifoASync
       generic map (
          TPD_G          => TPD_G,
+         RST_ASYNC_G    => RST_ASYNC_G,
          RST_POLARITY_G => '1',
          MEMORY_TYPE_G  => "distributed", -- Use Dist Ram
          FWFT_EN_G      => true,

axi/axi-lite/rtl/AxiLiteCrossbar.vhd

@@ -24,7 +24,6 @@ use surf.ArbiterPkg.all;
 use surf.TextUtilPkg.all;
 
 entity AxiLiteCrossbar is
-
    generic (
       TPD_G              : time                             := 1 ns;
       RST_ASYNC_G        : boolean                          := false;
@@ -175,7 +174,7 @@ begin
          case (r.slave(s).wrState) is
             when S_WAIT_AXI_TXN_S =>
 
-               -- Incomming write
+               -- Incoming write
                if (sAxiWriteMasters(s).awvalid = '1' and sAxiWriteMasters(s).wvalid = '1') then
 
                   for m in MASTERS_CONFIG_G'range loop
@@ -248,7 +247,7 @@ begin
          case (r.slave(s).rdState) is
             when S_WAIT_AXI_TXN_S =>
 
-               -- Incomming read
+               -- Incoming read
                if (sAxiReadMasters(s).arvalid = '1') then
                   for m in MASTERS_CONFIG_G'range loop
                      -- Check for address match
@@ -340,7 +339,7 @@ begin
                end if;
 
                -- Upon valid request (set 1 cycle previous by arbitrate()), connect slave side
-               -- busses to this master's outputs.
+               -- buses to this master's outputs.
                if (r.master(m).wrValid = '1') then
                   v.master(m).wrAcks    := r.master(m).wrAcks;
                   v.mAxiWriteMasters(m) := sAxiWriteMasters(conv_integer(r.master(m).wrAckNum));
@@ -397,7 +396,7 @@ begin
                end if;
 
                -- Upon valid request (set 1 cycle previous by arbitrate()), connect slave side
-               -- busses to this master's outputs.
+               -- buses to this master's outputs.
                if (r.master(m).rdValid = '1') then
                   v.master(m).rdAcks   := r.master(m).rdAcks;
                   v.mAxiReadMasters(m) := sAxiReadMasters(conv_integer(r.master(m).rdAckNum));

axi/axi-lite/rtl/AxiLiteFifoPop.vhd

@@ -5,12 +5,12 @@
 -- Supports reading of general purpose FIFOs from the AxiLite bus.
 -- One address location per FIFO.
 -- Address map depends on the POP and LOOP FIFO counts.
--- RANGE_LSB_G sets the address bit which seperates the
+-- RANGE_LSB_G sets the address bit which separates the
 -- POP FIFO address space from the loop FIFO address space.
 -- RANGE_LSB_G must be large enough for the number of POP and LOOP FIFOs
 -- enabled. I.E. if POP_FIFO_COUNT_C is 8, RANGE_FIFO_G must be > 5.
--- POP Fifos exist at 0x0, 0x4, 0x8, 0xC ...
--- LOOP Fifos exist at 2^(RANGE_LSB_C) + 0x0, + 0x4, etc.
+-- POP FIFOs exist at 0x0, 0x4, 0x8, 0xC ...
+-- LOOP FIFOs exist at 2^(RANGE_LSB_C) + 0x0, + 0x4, etc.
 -------------------------------------------------------------------------------
 -- This file is part of 'SLAC Firmware Standard Library'.
 -- It is subject to the license terms in the LICENSE.txt file found in the
@@ -23,9 +23,8 @@
 
 library ieee;
 use ieee.std_logic_1164.all;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
 
 library surf;
 use surf.StdRtlPkg.all;
@@ -34,6 +33,7 @@ use surf.AxiLitePkg.all;
 entity AxiLiteFifoPop is
    generic (
       TPD_G              : time                       := 1 ns;
+      RST_ASYNC_G        : boolean                    := true;
       POP_FIFO_COUNT_G   : positive                   := 1;
       POP_SYNC_FIFO_G    : boolean                    := false;
       POP_MEMORY_TYPE_G  : string                     := "block";
@@ -45,10 +45,8 @@ entity AxiLiteFifoPop is
       LOOP_ADDR_WIDTH_G  : integer range 4 to 48      := 4;
       RANGE_LSB_G        : integer range 0 to 31      := 8;
       VALID_POSITION_G   : integer range 0 to 31      := 0;
-      VALID_POLARITY_G   : sl                         := '0'
-   );
+      VALID_POLARITY_G   : sl                         := '0');
    port (
-
       -- AXI Interface (axiClk)
       axiClk             : in  sl;
       axiClkRst          : in  sl;
@@ -61,16 +59,14 @@ entity AxiLiteFifoPop is
       loopFifoValid      : out slv(LOOP_FIFO_COUNT_G-1 downto 0);
       loopFifoAEmpty     : out slv(LOOP_FIFO_COUNT_G-1 downto 0);
       loopFifoAFull      : out slv(LOOP_FIFO_COUNT_G-1 downto 0);
-
       -- POP FIFO Write Interface (popFifoClk)
       popFifoClk         : in  slv(POP_FIFO_COUNT_G-1 downto 0);
       popFifoRst         : in  slv(POP_FIFO_COUNT_G-1 downto 0);
       popFifoWrite       : in  slv(POP_FIFO_COUNT_G-1 downto 0);
       popFifoDin         : in  Slv32Array(POP_FIFO_COUNT_G-1 downto 0);
       popFifoFull        : out slv(POP_FIFO_COUNT_G-1 downto 0);
       popFifoAFull       : out slv(POP_FIFO_COUNT_G-1 downto 0);
-      popFifoPFull       : out slv(POP_FIFO_COUNT_G-1 downto 0)
-   );
+      popFifoPFull       : out slv(POP_FIFO_COUNT_G-1 downto 0));
 end AxiLiteFifoPop;
 
 architecture structure of AxiLiteFifoPop is
@@ -129,7 +125,7 @@ begin
             CASCADE_SIZE_G     => 1,
             LAST_STAGE_ASYNC_G => true,
             RST_POLARITY_G     => '1',
-            RST_ASYNC_G        => true,
+            RST_ASYNC_G        => RST_ASYNC_G,
             GEN_SYNC_FIFO_G    => POP_SYNC_FIFO_G,
             MEMORY_TYPE_G      => POP_MEMORY_TYPE_G,
             FWFT_EN_G          => true,
@@ -182,7 +178,7 @@ begin
                CASCADE_SIZE_G     => 1,
                LAST_STAGE_ASYNC_G => true,
                RST_POLARITY_G     => '1',
-               RST_ASYNC_G        => true,
+               RST_ASYNC_G        => RST_ASYNC_G,
                GEN_SYNC_FIFO_G    => true,
                MEMORY_TYPE_G      => LOOP_MEMORY_TYPE_G,
                FWFT_EN_G          => true,
@@ -237,15 +233,6 @@ begin
    -- AXI Lite
    -----------------------------------------
 
-   -- Sync
-   process (axiClk) is
-   begin
-      if (rising_edge(axiClk)) then
-         r <= rin after TPD_G;
-      end if;
-   end process;
-
-   -- Async
    process (r, axiClkRst, axiReadMaster, axiWriteMaster, ipopFifoDout, ipopFifoValid, iloopFifoDout, iloopFifoValid ) is
       variable v         : RegType;
       variable axiStatus : AxiLiteStatusType;
@@ -303,7 +290,7 @@ begin
       end if;
 
       -- Reset
-      if (axiClkRst = '1') then
+      if (RST_ASYNC_G = false and axiClkRst = '1') then
          v := REG_INIT_C;
       end if;
 
@@ -320,5 +307,13 @@ begin
 
    end process;
 
-end architecture structure;
+   seq : process (axiClk, axiClkRst) is
+   begin
+      if (RST_ASYNC_G and axiClkRst = '1') then
+         r <= REG_INIT_C after TPD_G;
+      elsif rising_edge(axiClk) then
+         r <= rin after TPD_G;
+      end if;
+   end process seq;
 
+end architecture structure;