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Add regression tests for assignment operator on queue and darray elem…
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Check that assignment operators work as expected on queue and dynamic array
elements.

Signed-off-by: Lars-Peter Clausen <[email protected]>
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larsclausen committed Jan 3, 2025
1 parent ec006e0 commit 7029797
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86 changes: 86 additions & 0 deletions ivtest/ivltests/sv_darray_assign_op.v
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@@ -0,0 +1,86 @@
// Check that assignment operators are supported on dynamic array elements.

module test;

bit failed = 1'b0;

`define check(val, exp) do \
if (val !== exp) begin \
$display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, `"val`", exp, val); \
failed = 1'b1; \
end \
while(0)

integer x[];
integer i;

initial begin
x = new[2];

// Static index
x[1] = 1;
x[1] += 5;
`check(x[1], 6);
x[1] -= 2;
`check(x[1], 4);
x[1] *= 25;
`check(x[1], 100);
x[1] /= 5;
`check(x[1], 20);
x[1] %= 3;
`check(x[1], 2);

x[1] = 'haa;
x[1] &= 'h33;
`check(x[1], 'h22);
x[1] |= 'h11;
`check(x[1], 'h33);
x[1] ^= 'h22;
`check(x[1], 'h11);

x[1] <<= 3;
`check(x[1], 'h88);
x[1] <<<= 1;
`check(x[1], 'h110);
x[1] >>= 2;
`check(x[1], 'h44);
x[1] >>>= 1;
`check(x[1], 'h22);

// Dynamic index
x[1] = 1;
i = 1;
x[i] += 5;
`check(x[i], 6);
x[i] -= 2;
`check(x[i], 4);
x[i] *= 25;
`check(x[i], 100);
x[i] /= 5;
`check(x[i], 20);
x[i] %= 3;
`check(x[i], 2);

x[i] = 'haa;
x[i] &= 'h33;
`check(x[i], 'h22);
x[i] |= 'h11;
`check(x[i], 'h33);
x[i] ^= 'h22;
`check(x[i], 'h11);

x[i] <<= 3;
`check(x[i], 'h88);
x[i] <<<= 1;
`check(x[i], 'h110);
x[i] >>= 2;
`check(x[i], 'h44);
x[i] >>>= 1;
`check(x[i], 'h22);

if (!failed) begin
$display("PASSED");
end
end

endmodule
84 changes: 84 additions & 0 deletions ivtest/ivltests/sv_queue_assign_op.v
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@@ -0,0 +1,84 @@
// Check that assignment operators are supported on queue elements.

module test;

bit failed = 1'b0;

`define check(val, exp) do \
if (val !== exp) begin \
$display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, `"val`", exp, val); \
failed = 1'b1; \
end \
while(0)

integer x[$];
integer i;

initial begin
x = '{0, 1};
// Static index
x[1] += 5;
`check(x[1], 6);
x[1] -= 2;
`check(x[1], 4);
x[1] *= 25;
`check(x[1], 100);
x[1] /= 5;
`check(x[1], 20);
x[1] %= 3;
`check(x[1], 2);

x[1] = 'haa;
x[1] &= 'h33;
`check(x[1], 'h22);
x[1] |= 'h11;
`check(x[1], 'h33);
x[1] ^= 'h22;
`check(x[1], 'h11);

x[1] <<= 3;
`check(x[1], 'h88);
x[1] <<<= 1;
`check(x[1], 'h110);
x[1] >>= 2;
`check(x[1], 'h44);
x[1] >>>= 1;
`check(x[1], 'h22);

// Dynamic index
x[1] = 1;
i = 1;
x[i] += 5;
`check(x[i], 6);
x[i] -= 2;
`check(x[i], 4);
x[i] *= 25;
`check(x[i], 100);
x[i] /= 5;
`check(x[i], 20);
x[i] %= 3;
`check(x[i], 2);

x[i] = 'haa;
x[i] &= 'h33;
`check(x[i], 'h22);
x[i] |= 'h11;
`check(x[i], 'h33);
x[i] ^= 'h22;
`check(x[i], 'h11);

x[i] <<= 3;
`check(x[i], 'h88);
x[i] <<<= 1;
`check(x[i], 'h110);
x[i] >>= 2;
`check(x[i], 'h44);
x[i] >>>= 1;
`check(x[i], 'h22);

if (!failed) begin
$display("PASSED");
end
end

endmodule
2 changes: 2 additions & 0 deletions ivtest/regress-vvp.list
Original file line number Diff line number Diff line change
Expand Up @@ -238,6 +238,7 @@ sv_const_fail6 vvp_tests/sv_const_fail6.json
sv_const_fail7 vvp_tests/sv_const_fail7.json
sv_const_fail8 vvp_tests/sv_const_fail8.json
sv_const_fail9 vvp_tests/sv_const_fail9.json
sv_darray_assign_op vvp_tests/sv_darray_assign_op.json
sv_default_port_value1 vvp_tests/sv_default_port_value1.json
sv_default_port_value2 vvp_tests/sv_default_port_value2.json
sv_default_port_value3 vvp_tests/sv_default_port_value3.json
Expand All @@ -256,6 +257,7 @@ sv_module_port2 vvp_tests/sv_module_port2.json
sv_module_port3 vvp_tests/sv_module_port3.json
sv_module_port4 vvp_tests/sv_module_port4.json
sv_parameter_type vvp_tests/sv_parameter_type.json
sv_queue_assign_op vvp_tests/sv_queue_assign_op.json
sv_wildcard_import8 vvp_tests/sv_wildcard_import8.json
sdf_header vvp_tests/sdf_header.json
task_return1 vvp_tests/task_return1.json
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5 changes: 5 additions & 0 deletions ivtest/vvp_tests/sv_darray_assign_op.json
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@@ -0,0 +1,5 @@
{
"type" : "normal",
"source" : "sv_darray_assign_op.v",
"iverilog-args" : [ "-g2005-sv" ]
}
5 changes: 5 additions & 0 deletions ivtest/vvp_tests/sv_queue_assign_op.json
Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
{
"type" : "normal",
"source" : "sv_queue_assign_op.v",
"iverilog-args" : [ "-g2005-sv" ]
}
1 change: 1 addition & 0 deletions tgt-vvp/stmt_assign.c
Original file line number Diff line number Diff line change
Expand Up @@ -1061,6 +1061,7 @@ static void show_stmt_assign_sig_darray_queue_mux(ivl_statement_t net)
case IVL_VT_STRING:
assert(ivl_stmt_opcode(net) == 0);
draw_eval_string(rval);
draw_eval_expr_into_integer(mux, 3);
break;
case IVL_VT_BOOL:
case IVL_VT_LOGIC:
Expand Down

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