Add initial support for array assignment patterns #953
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For indexed array properties the type of the expression is the type of the element. Signed-off-by: Lars-Peter Clausen <[email protected]>
Types for array signals are currently handled as a special case. The type that is associated with the signal is not the array type itself but rather the element type. There is a fair amount of existing code that depends on this behavior so it is not trivial to change this. But there are certain constructs such as assignment patterns or array concatenation where the array type itself is required. Add a new `NetNet::array_type()` method that will return the array type if the signal is an array. This will allow to query the array type when needed. `NetAssign_::net_type()` is updated to use this new method to return the array type if the assigned signal is an array. Long term the special handling of arrays for signals should be removed. This will for example allow to unify the handling of arrays for signals, class properties and struct members. Signed-off-by: Lars-Peter Clausen <[email protected]>
SystemVerilog allows to use assignment patterns to assign values to an
array. E.g. `int a[4] = '{1, 2, 3, 4}`.
Each value is evaluated in the context of the element type of the array.
Nested assignment patterns are supported. E.g. `int a[2][2] = '{'{1, 2},
'{1, 2}};`
Add initial support for array assignment patterns for both continuous as
well as procedural assignments.
For continuous assignments the assignment pattern is synthesized into an
array of nets. Each pin is connected to one of the assignment pattern
values and then the whole net array is connected to target array.
For procedural assignments it is unrolled in the vvp backend. E.g
effectively turning `a = '{1, 2};` into `a[0] = 1; a[1] = 2;`.
Not yet supported are indexed initializers or `default`.
E.g. `int a[10] = '{1:10, default: 20};`
Signed-off-by: Lars-Peter Clausen <[email protected]>
Check that basic assignment patterns are supported for unpacked arrays. Check that all of packed types, reals and string arrays are supported. Signed-off-by: Lars-Peter Clausen <[email protected]>
Check that trying to assign a scalar value to an array results in an error. Signed-off-by: Lars-Peter Clausen <[email protected]>
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SystemVerilog allows to use assignment patterns to assign values to an
array. E.g.
int a[4] = '{1, 2, 3, 4}.Each value is evaluated in the context of the element type of the array.
Nested assignment patterns are supported. E.g.
int a[2][2] = '{'{1, 2}, '{1, 2}};Add initial support for array assignment patterns for both continuous as
well as procedural assignments.
For continuous assignments the assignment pattern is synthesized into an
array of nets. Each pin is connected to one of the assignment pattern
values and then the whole net array is connected to target array.
For procedural assignments it is unrolled in the vvp backend. E.g
effectively turning
a = '{1, 2};intoa[0] = 1; a[1] = 2;.Not yet supported are indexed initializers or
default.E.g.
int a[10] = '{1:10, default: 20};Resolves #562