Update coreboot

- Leave TBT LSX0 as FSP configured - Select CBFS SMBIOS hooks - Hook up microcode for CML-S - Move RPL-HX power limits to correct file Signed-off-by: Tim Crawford <[email protected]>
system76 · Jul 17, 2023 · 200ddc0 · 200ddc0
1 parent 0e4a64a
commit 200ddc0
Show file tree

Hide file tree

Showing 2 changed files with 6 additions and 1 deletion.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -6,6 +6,11 @@ date followed by an underscore and a short git revision. To see if specific
 features apply to your model and firmware version, see the
 [feature matrix](./FEATURES.md).
 
+## unreleased
+
+- bonw14: Updated microcode to revision 0xf4
+- rpl-hx: Fixed setting PL1 and PL2 power limits
+
 ## 2023-07-10
 
 - Updated Secure Boot DBX to version 371 (2023-05-09)

diff --git a/coreboot b/coreboot
+2 −0		src/mainboard/system76/addw1/Kconfig
+2 −0		src/mainboard/system76/adl/Kconfig
+2 −2		src/mainboard/system76/adl/variants/gaze17-3060-b/gpio.c
+2 −0		src/mainboard/system76/bonw14/Kconfig
+2 −0		src/mainboard/system76/cml-u/Kconfig
+2 −0		src/mainboard/system76/gaze15/Kconfig
+2 −0		src/mainboard/system76/kbl-u/Kconfig
+2 −0		src/mainboard/system76/oryp5/Kconfig
+2 −0		src/mainboard/system76/oryp6/Kconfig
+2 −0		src/mainboard/system76/rpl/Kconfig
+2 −2		src/mainboard/system76/rpl/variants/oryp11/gpio.c
+2 −0		src/mainboard/system76/tgl-h/Kconfig
+2 −2		src/mainboard/system76/tgl-h/variants/oryp8/gpio.c
+2 −0		src/mainboard/system76/tgl-u/Kconfig
+2 −0		src/mainboard/system76/whl-u/Kconfig
+0 −30		src/soc/intel/alderlake/chipset.cb
+30 −0		src/soc/intel/alderlake/chipset_pch_s.cb
+2 −0		src/soc/intel/cannonlake/Makefile.inc