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make clean
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@taiyoslime
taiyoslime committed Dec 6, 2020
1 parent f2dfbba commit 32ea6f7
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1 change: 1 addition & 0 deletions .gitignore
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obj/
156 changes: 78 additions & 78 deletions alu.sv
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`include "define.vh"

module alu(
input logic [5:0] alucode,
input logic [31:0] op1,
input logic [31:0] op2,
output logic [31:0] alu_result,
output logic br_taken
);
always @(*) begin
case (alucode)
`ALU_ADD, `ALU_LB, `ALU_LH, `ALU_LW, `ALU_LBU, `ALU_LHU, `ALU_SB, `ALU_SH, `ALU_SW: begin
alu_result = op1 + op2;
br_taken = `DISABLE;
end
`ALU_SUB: begin
alu_result = op1 - op2;
br_taken = `DISABLE;
end
`ALU_SLL: begin
alu_result = op1 << op2[4:0]; // op2[4:0]
br_taken = `DISABLE;
end
`ALU_SLT: begin
alu_result = {31'b0, $signed(op1) < $signed(op2)};
br_taken = `DISABLE;
end
`ALU_SLTU: begin
alu_result = {31'b0, op1 < op2};
br_taken = `DISABLE;
end
`ALU_XOR: begin
alu_result = op1 ^ op2;
br_taken = `DISABLE;
end
`ALU_SRL: begin
alu_result = op1 >> op2[4:0]; // op2[4:0]
br_taken = `DISABLE;
end
`ALU_SRA: begin
alu_result = $signed(op1) >>> $signed(op2[4:0]); // op2[4:0]
br_taken = `DISABLE;
end
`ALU_OR: begin
alu_result = op1 | op2;
br_taken = `DISABLE;
end
`ALU_AND: begin
alu_result = op1 & op2;
br_taken = `DISABLE;
end
`ALU_LUI: begin
alu_result = op2;
br_taken = `DISABLE;
end
`ALU_JAL: begin
alu_result = op2 + 32'h4;
br_taken = `ENABLE;
end
`ALU_JALR: begin
alu_result = op2 + 32'h4;
br_taken = `ENABLE;
end
`ALU_BEQ, `ALU_BNE, `ALU_BLT, `ALU_BGE, `ALU_BLTU, `ALU_BGEU: begin
alu_result = 32'b0;
case (alucode)
`ALU_BEQ: br_taken = op1 == op2 ? `ENABLE : `DISABLE;
`ALU_BNE: br_taken = op1 == op2 ? `DISABLE : `ENABLE;
`ALU_BLT: br_taken = $signed(op1) < $signed(op2) ? `ENABLE : `DISABLE;
`ALU_BGE: br_taken = $signed(op1) < $signed(op2) ? `DISABLE : `ENABLE;
`ALU_BLTU: br_taken = op1 < op2 ? `ENABLE : `DISABLE;
`ALU_BGEU: br_taken = op1 < op2 ? `DISABLE : `ENABLE;
default: ;
endcase
end
default: ;
endcase
end
input logic [5:0] alucode,
input logic [31:0] op1,
input logic [31:0] op2,
output logic [31:0] alu_result,
output logic br_taken
);

always_latch begin
case (alucode)
`ALU_ADD, `ALU_LB, `ALU_LH, `ALU_LW, `ALU_LBU, `ALU_LHU, `ALU_SB, `ALU_SH, `ALU_SW: begin
alu_result = op1 + op2;
br_taken = `DISABLE;
end
`ALU_SUB: begin
alu_result = op1 - op2;
br_taken = `DISABLE;
end
`ALU_SLL: begin
alu_result = op1 << op2[4:0]; // op2[4:0]
br_taken = `DISABLE;
end
`ALU_SLT: begin
alu_result = {31'b0, $signed(op1) < $signed(op2)};
br_taken = `DISABLE;
end
`ALU_SLTU: begin
alu_result = {31'b0, op1 < op2};
br_taken = `DISABLE;
end
`ALU_XOR: begin
alu_result = op1 ^ op2;
br_taken = `DISABLE;
end
`ALU_SRL: begin
alu_result = op1 >> op2[4:0]; // op2[4:0]
br_taken = `DISABLE;
end

`ALU_SRA: begin
alu_result = $signed(op1) >>> $signed(op2[4:0]); // op2[4:0]
br_taken = `DISABLE;
end

`ALU_OR: begin
alu_result = op1 | op2;
br_taken = `DISABLE;
end
`ALU_AND: begin
alu_result = op1 & op2;
br_taken = `DISABLE;
end
`ALU_LUI: begin
alu_result = op2;
br_taken = `DISABLE;
end
`ALU_JAL: begin
alu_result = op2 + 32'h4;
br_taken = `ENABLE;
end
`ALU_JALR: begin
alu_result = op2 + 32'h4;
br_taken = `ENABLE;
end
`ALU_BEQ, `ALU_BNE, `ALU_BLT, `ALU_BGE, `ALU_BLTU, `ALU_BGEU: begin
alu_result = 32'b0;
case (alucode)
`ALU_BEQ: br_taken = op1 == op2 ? `ENABLE : `DISABLE;
`ALU_BNE: br_taken = op1 == op2 ? `DISABLE : `ENABLE;
`ALU_BLT: br_taken = $signed(op1) < $signed(op2) ? `ENABLE : `DISABLE;
`ALU_BGE: br_taken = $signed(op1) < $signed(op2) ? `DISABLE : `ENABLE;
`ALU_BLTU: br_taken = op1 < op2 ? `ENABLE : `DISABLE;
`ALU_BGEU: br_taken = op1 < op2 ? `DISABLE : `ENABLE;
default: ;
endcase
end
default: ;
endcase
end

endmodule
220 changes: 107 additions & 113 deletions core.sv
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`include "define.vh"

module core(
input logic clk,
input logic rst,
output uart_tx
);

logic [4:0] pipeline_clk;
//logic pe;

initial begin
pipeline_clk = 5'b10000;
//pe = 0;
end

logic [31:0] pc;
logic [31:0] inst;

always @(posedge clk or negedge rst) begin
if(!rst) begin
pipeline_clk <= 5'b10000;
end else begin
pipeline_clk <= pipeline_clk != 5'b10000 ? (pipeline_clk << 1) : 5'b00001;
end
// if (pc == 'h8004) begin
// pe <= 1;
// end
end


fetch fetch(
.clk(pipeline_clk[0]),
.*
);

logic reg_we;

logic [31:0] rs1;
logic [31:0] rs2;
logic [31:0] rd;
logic [4:0] rs1_src;
logic [4:0] rs2_src;
logic [4:0] rd_src;


regfile regfile(
.*
);

logic [31:0] imm;
logic [5:0] alucode;
logic [1:0] aluop1_type;
logic [1:0] aluop2_type;
logic is_load;
logic is_store;
logic is_halt;

decoder decoder(
.clk(pipeline_clk[1]),
.*
);


logic [31:0] pc_next;
logic [31:0] alu_result;

execute execute(
.clk(pipeline_clk[2]),
.*
);

logic [31:0] data_r;
logic [31:0] data_w;
assign data_w = rs2;
logic [31:0] addr_w, addr_r;
assign addr_w = alu_result;
assign addr_r = alu_result;

data_mem data_mem(
.clk(pipeline_clk[3]),
.*
);

write write(
.clk(pipeline_clk[4]),
.*
);

wire [7:0] uart_IN_data;
wire uart_we;
wire uart_OUT_data;

uart uart0(
.uart_tx(uart_OUT_data),
.uart_wr_i(uart_we),
.uart_dat_i(uart_IN_data),
.sys_clk_i(clk),
.sys_rstn_i(rst)
);

assign uart_IN_data = data_w[7:0]; // �X�g�A����f�[�^�����W���[���֓���
assign uart_we = ((addr_w == `UART_ADDR) && (is_store == `ENABLE)) ? 1'b1 : 1'b0; // �V���A���ʐM�p�A�h���X�ւ̃X�g�A���ߎ��s���ɑ��M�J�n�M�����A�T�[�g
assign uart_tx = uart_OUT_data; // �V���A���ʐM���W���[���̏o�͂�FPGA�O���ւƏo��


wire [31:0] hc_OUT_data;

hardware_counter hardware_counter0(
//.CLK_IP(pipeline_clk == 5'b00001 ),
.CLK_IP(clk),
.RSTN_IP(rst),
.COUNTER_OP(hc_OUT_data)
);

assign rd = ((alucode == `ALU_LW) && (addr_w == `HARDWARE_COUNTER_ADDR)) ? hc_OUT_data : is_load == `ENABLE ? data_r : alu_result;
input logic clk,
input logic rst,
output uart_tx
);

logic [4:0] pipeline_clk;

initial begin
pipeline_clk = 5'b10000;
end

logic [31:0] pc;
logic [31:0] inst;

always @(posedge clk or negedge rst) begin
if(!rst) begin
pipeline_clk <= 5'b10000;
end else begin
pipeline_clk <= pipeline_clk != 5'b10000 ? (pipeline_clk << 1) : 5'b00001;
end
end


fetch fetch(
.clk(pipeline_clk[0]),
.*
);

logic reg_we;

logic [31:0] rs1;
logic [31:0] rs2;
logic [31:0] rd;
logic [4:0] rs1_src;
logic [4:0] rs2_src;
logic [4:0] rd_src;


regfile regfile(
.*
);

logic [31:0] imm;
logic [5:0] alucode;
logic [1:0] aluop1_type;
logic [1:0] aluop2_type;
logic is_load;
logic is_store;
logic is_halt;

decoder decoder(
.clk(pipeline_clk[1]),
.*
);


logic [31:0] pc_next;
logic [31:0] alu_result;

execute execute(
.clk(pipeline_clk[2]),
.*
);

logic [31:0] data_r;
logic [31:0] data_w;
assign data_w = rs2;
logic [31:0] addr_w, addr_r;
assign addr_w = alu_result;
assign addr_r = alu_result;

data_mem data_mem(
.clk(pipeline_clk[3]),
.*
);

write write(
.clk(pipeline_clk[4]),
.*
);

wire [7:0] uart_IN_data;
wire uart_we;
wire uart_OUT_data;

uart uart0(
.uart_tx(uart_OUT_data),
.uart_wr_i(uart_we),
.uart_dat_i(uart_IN_data),
.sys_clk_i(clk),
.sys_rstn_i(rst)
);

assign uart_IN_data = data_w[7:0];
assign uart_we = ((addr_w == `UART_ADDR) && (is_store == `ENABLE)) ? 1'b1 : 1'b0;
assign uart_tx = uart_OUT_data;


wire [31:0] hc_OUT_data;

hardware_counter hardware_counter0(
.CLK_IP(clk),
.RSTN_IP(rst),
.COUNTER_OP(hc_OUT_data)
);

assign rd = ((alucode == `ALU_LW) && (addr_w == `HARDWARE_COUNTER_ADDR)) ? hc_OUT_data : is_load == `ENABLE ? data_r : alu_result;

endmodule
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