Add PC verilog version

verilog/PC.v

@@ -0,0 +1,27 @@
+module PC (
+        input clk,              // clock
+        input rst,              // active high reset
+        input [7:0] jmpAddr,    // jump destination Addr
+        // control signals
+        input branch,
+        input ijump,
+        input aluFlag,
+        input wPC,
+        // output: register value
+        output reg [7:0] PC
+    );
+
+    // initial PC=0;
+
+    always @(posedge clk) begin
+        if(rst)
+            PC <= 8'h00;
+        else if(wPC) begin
+            if( branch && ( ijump || aluFlag ) ) 
+                PC <= jmpAddr;
+            else 
+                PC <= PC + 1;
+        end
+    end
+
+endmodule

verilog/PC_tb.gtkw

@@ -0,0 +1,37 @@
+[*]
+[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
+[*] Sun Apr 15 14:40:52 2018
+[*]
+[dumpfile] "/home/adumont/projects/hrm-cpu/verilog/PC_tb.vcd"
+[dumpfile_mtime] "Sun Apr 15 14:37:54 2018"
+[dumpfile_size] 1138
+[savefile] "/home/adumont/projects/hrm-cpu/verilog/PC_tb.gtkw"
+[timestart] 0
+[size] 1678 998
+[pos] -1 -1
+*-4.951978 50 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] PC_tb.
+[sst_width] 197
+[signals_width] 155
+[sst_expanded] 1
+[sst_vpaned_height] 299
+@28
+PC_tb.clk
+@200
+-
+@29
+PC_tb.PC0.rst
+@28
+PC_tb.PC0.wPC
+@200
+-
+@28
+PC_tb.branch
+PC_tb.ijump
+PC_tb.aluFlag
+@200
+-
+@22
+PC_tb.PC[7:0]
+[pattern_trace] 1
+[pattern_trace] 0

verilog/PC_tb.v

@@ -0,0 +1,92 @@
+module PC_tb;
+
+    reg clk  = 0;
+    reg rst = 0;
+    reg branch = 0;
+    reg ijump = 0;
+    reg aluFlag = 0;
+    reg wPC = 0;
+
+    reg  [7:0] jmpAddr = 8'b00;
+    wire [7:0] PC;
+
+    // Instanciate DUT
+    PC PC0 (
+        .clk(clk),
+        .rst(rst),
+        .jmpAddr(jmpAddr),
+        .branch(branch),
+        .ijump(ijump),
+        .aluFlag(aluFlag),
+        .wPC(wPC),
+        .PC(PC)
+    );
+
+    // Simulate clock
+    always #4 clk = ~clk;
+
+    // Start simulation
+    initial begin
+
+        $dumpfile("PC_tb.vcd");
+        $dumpvars(0, PC_tb);
+
+        #2 
+
+        #1  rst = 1;
+        #2  rst = 0;
+
+        #6  wPC = 1;
+        #2  wPC = 0;
+
+    // JUMP
+        #4  branch=1;
+            ijump=1;
+            aluFlag = 0;    // should jump to B0
+            jmpAddr = 8'hB2;
+
+        #2  wPC = 1;
+        #2  wPC = 0;            
+
+
+    // INCRPC
+        #4  branch=0;
+            ijump=0;
+            aluFlag = 0;
+            jmpAddr = 8'h00; // doesn't matter...
+
+        #2  wPC = 1;
+        #2  wPC = 0;            
+
+    // INCRPC
+        #4  branch=0;
+            ijump=0;
+            aluFlag = 0;
+            jmpAddr = 8'h00; // doesn't matter...
+
+        #2  wPC = 1;
+        #2  wPC = 0;            
+
+    // JUMPZ/N
+        #4  branch=1;
+            ijump=0;
+            aluFlag = 1;    // should jump to A0
+            jmpAddr = 8'hA0;
+
+        #2  wPC = 1;
+        #2  wPC = 0;            
+
+    // JUMPZ/N
+        #4  branch=1;
+            ijump=0;
+            aluFlag = 0;    // should NOT jump to A0 --> A0 +1 => A1
+            jmpAddr = 8'hA0;
+
+        #2  wPC = 1;
+        #2  wPC = 0;            
+
+        #10 $finish;
+    end
+
+
+endmodule