Fvp Base Fixes

ArmPkg/Drivers/ArmGic/ArmGicLib.c

@@ -280,15 +280,31 @@ ArmGicDisableDistributor (
 VOID
 EFIAPI
 ArmGicEnableInterruptInterface (
-  IN  INTN          GicInterruptInterfaceBase
+  IN  INTN          GicInterruptInterfaceBase,
+  IN  INTN          GicRedistributorBase
   )
 {
   ARM_GIC_ARCH_REVISION Revision;
+  UINTN                 GicCpuRedistributorBase;
 
   Revision = ArmGicGetSupportedArchRevision ();
   if (Revision == ARM_GIC_ARCH_REVISION_2) {
     ArmGicV2EnableInterruptInterface (GicInterruptInterfaceBase);
   } else if (Revision == ARM_GIC_ARCH_REVISION_3) {
+
+    if (GicRedistributorBase != 0) {
+      GicCpuRedistributorBase = GicGetCpuRedistributorBase(GicRedistributorBase, Revision);
+      if (GicCpuRedistributorBase == 0) {
+        ASSERT_EFI_ERROR(EFI_NOT_FOUND);
+        return;
+      }
+
+      // The ProcessorSleep bit in the redistributor must be cleared for interrupts to be delivered
+      // this must be done regardless of whether we're running in a GICv2 compatible mode.
+      // This write only takes effect in secure mode and is ignored in non-secure mode.
+      MmioAnd32(GicCpuRedistributorBase + ARM_GICR_WAKER, ~ARM_GICR_WAKER_PS);
+    }
+
     ArmGicV3EnableInterruptInterface ();
   } else {
     ASSERT_EFI_ERROR (EFI_UNSUPPORTED);

ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c

@@ -305,7 +305,7 @@ GicV2DxeInitialize (
   MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0xff);
 
   // Enable gic cpu interface
-  ArmGicEnableInterruptInterface (mGicInterruptInterfaceBase);
+  ArmGicEnableInterruptInterface (mGicInterruptInterfaceBase, 0);
 
   // Enable gic distributor
   ArmGicEnableDistributor (mGicDistributorBase);

ArmPkg/Include/Library/ArmGicLib.h

@@ -65,6 +65,10 @@ typedef enum {
 
 // GIC Redistributor Control frame
 #define ARM_GICR_TYPER          0x0008  // Redistributor Type Register
+#define ARM_GICR_WAKER          0x0014  // Redistributors Wake Request Register
+
+// GIC Redistributor WAKER fields
+#define ARM_GICR_WAKER_PS       0x00000002  // ProcessorSleep
 
 // GIC SGI & PPI Redistributor frame
 #define ARM_GICR_ISENABLER      0x0100  // Interrupt Set-Enable Registers
@@ -136,9 +140,10 @@ ArmGicSetSecureInterrupts (
 
 VOID
 EFIAPI
-ArmGicEnableInterruptInterface (
-  IN  INTN          GicInterruptInterfaceBase
-  );
+ArmGicEnableInterruptInterface(
+  IN  INTN          GicInterruptInterfaceBase,
+  IN  INTN          GicRedistributorBase
+);
 
 VOID
 EFIAPI

ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc

@@ -119,9 +119,9 @@
   gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000
   gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000
 
-  # System Memory (2GB - 16MB of Trusted DRAM at the top of the 32bit address space)
-  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
-  gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000
+  # System Memory (2GB of memory starting at 0x880000000)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x880000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
 
   # Size of the region used by UEFI in permanent memory (Reserved 64MB)
   gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000

ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h

@@ -51,6 +51,10 @@
 // This can be any value since we only support motherboard PL111
 #define LCD_VRAM_CORE_TILE_BASE                 0x00000000
 
+// TZC-400 Address Space Controller
+#define ARM_REFCNT_BASE                         0x2a430000
+#define ARM_VE_TZC400_BASE                      0x2a4a0000
+
 // On-chip peripherals (Snoop Control Unit etc...)
 #define ARM_VE_ON_CHIP_PERIPH_BASE              0x2C000000
 // Note: The TRM says not all the peripherals are implemented

ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/RTSMSec.c

@@ -41,7 +41,19 @@ ArmPlatformSecTrustzoneInit (
   IN  UINTN                     MpId
   )
 {
-  // No TZPC or TZASC on RTSM to initialize
+  // Initialize TSC-400 to open all DRAM below 4G to nonsecure world
+
+  // configure security errors to be bus errors (data/prefetch aborts);
+  MmioWrite32(ARM_VE_TZC400_BASE + 0x004, 0x01);
+
+  // enable gate keepers for all four filter enables
+  MmioWrite32(ARM_VE_TZC400_BASE + 0x008, BIT3 | BIT2 | BIT1 | BIT0);
+
+  // enable secure reads and writes to region 0 - s_wr_en, s_rd_en
+  MmioOr32(ARM_VE_TZC400_BASE + 0x110, BIT31 | BIT30);
+
+  // enable all IDs to do non-secure read and writes
+  MmioWrite32(ARM_VE_TZC400_BASE + 0x114, 0xFFFFFFFF);
 }
 
 /**
@@ -72,6 +84,9 @@ ArmPlatformSecInitialize (
   // Configure SP810 to use 1MHz clock and disable
   MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
 
+  // start the base FVP reference counter
+  MmioOr32(ARM_REFCNT_BASE + 0, 0x01);
+
   // Read the GIC Identification Register
   Identification = ArmGicGetInterfaceIdentification (PcdGet32 (PcdGicInterruptInterfaceBase));
 

ArmPlatformPkg/Sec/Sec.c

@@ -85,10 +85,10 @@ CEntryPoint (
     // - no other Interrupts are enabled,  doesn't have to worry about the priority.
     // - all the cores are in secure state, use secure SGI's
     ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
-    ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
+    ArmGicEnableInterruptInterface(PcdGet32(PcdGicInterruptInterfaceBase), PcdGet32(PcdGicRedistributorsBase));
   } else {
     // Enable the GIC CPU Interface
-    ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
+    ArmGicEnableInterruptInterface(PcdGet32(PcdGicInterruptInterfaceBase), PcdGet32(PcdGicRedistributorsBase));
   }
 
   // Enable Full Access to CoProcessors

ArmPlatformPkg/Sec/Sec.inf

@@ -76,6 +76,7 @@
   gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize
 
   gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
 
   gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize