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Fix stm32f103 ADC #4702

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Jan 16, 2025
Merged

Fix stm32f103 ADC #4702

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7d55cae
Fix stm32f103 ADC
grudzinski Jan 15, 2025
f837e94
More ADC fixes
grudzinski Jan 15, 2025
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17 changes: 1 addition & 16 deletions src/machine/machine_stm32_adc_f1.go
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Original file line number Diff line number Diff line change
Expand Up @@ -23,15 +23,6 @@ func InitADC() {
// Enable ADC clock
enableAltFuncClock(unsafe.Pointer(stm32.ADC1))

// set scan mode
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After the chip reset the ADC is already configured for "Single conversion mode". Scan mode is relevant when DMA is used.

stm32.ADC1.CR1.SetBits(stm32.ADC_CR1_SCAN)

// clear CONT, ALIGN, EXTRIG and EXTSEL bits from CR2
stm32.ADC1.CR2.ClearBits(stm32.ADC_CR2_CONT | stm32.ADC_CR2_ALIGN | stm32.ADC_CR2_EXTTRIG_Msk | stm32.ADC_CR2_EXTSEL_Msk)

stm32.ADC1.SQR1.ClearBits(stm32.ADC_SQR1_L_Msk)
stm32.ADC1.SQR1.SetBits(2 << stm32.ADC_SQR1_L_Pos) // 2 means 3 conversions

// enable
stm32.ADC1.CR2.SetBits(stm32.ADC_CR2_ADON)
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First switch ON the ADC, only now we can touch the ADC registers


Expand Down Expand Up @@ -61,7 +52,7 @@ func (a ADC) Get() uint16 {
stm32.ADC1.SQR3.SetBits(ch)

// start conversion
stm32.ADC1.CR2.SetBits(stm32.ADC_CR2_SWSTART)
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It work only if EXTTRIG is enabled and SWSTART is selected in EXTSEL.

stm32.ADC1.CR2.SetBits(stm32.ADC_CR2_ADON)

// wait for conversion to complete
for !stm32.ADC1.SR.HasBits(stm32.ADC_SR_EOC) {
Expand All @@ -70,12 +61,6 @@ func (a ADC) Get() uint16 {
// read result as 16 bit value
result := uint16(stm32.ADC1.DR.Get()) << 4

// clear flag
stm32.ADC1.SR.ClearBits(stm32.ADC_SR_EOC)
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EOC is cleared by reading the ADC_DR.


// clear rank
stm32.ADC1.SQR3.ClearBits(ch)
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Redundant. It sets it to 0, means 0 channel.


return result
}

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13 changes: 9 additions & 4 deletions src/machine/machine_stm32f103.go
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Expand Up @@ -221,14 +221,19 @@ func (p Pin) enableClock() {

// Enable peripheral clock. Expand to include all the desired peripherals
func enableAltFuncClock(bus unsafe.Pointer) {
if bus == unsafe.Pointer(stm32.USART1) {
switch bus {
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❤️

case unsafe.Pointer(stm32.USART1):
stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN)
} else if bus == unsafe.Pointer(stm32.USART2) {
case unsafe.Pointer(stm32.USART2):
stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART2EN)
} else if bus == unsafe.Pointer(stm32.I2C1) {
case unsafe.Pointer(stm32.I2C1):
stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C1EN)
} else if bus == unsafe.Pointer(stm32.SPI1) {
case unsafe.Pointer(stm32.SPI1):
stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN)
case unsafe.Pointer(stm32.ADC1):
stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC1EN)
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Enable clock for ADC1

default:
panic("machine: unknown peripheral")
}
}

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9 changes: 5 additions & 4 deletions src/runtime/runtime_stm32f103.go
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Expand Up @@ -33,10 +33,11 @@ func buffered() int {

// initCLK sets clock to 72MHz using HSE 8MHz crystal w/ PLL X 9 (8MHz x 9 = 72MHz).
func initCLK() {
stm32.FLASH.ACR.SetBits(stm32.FLASH_ACR_LATENCY_WS2) // Two wait states, per datasheet
stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE1_Div2 << stm32.RCC_CFGR_PPRE1_Pos) // prescale PCLK1 = HCLK/2
stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE2_Div1 << stm32.RCC_CFGR_PPRE2_Pos) // prescale PCLK2 = HCLK/1
stm32.RCC.CR.SetBits(stm32.RCC_CR_HSEON) // enable HSE clock
stm32.FLASH.ACR.SetBits(stm32.FLASH_ACR_LATENCY_WS2) // Two wait states, per datasheet
stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE1_Div2 << stm32.RCC_CFGR_PPRE1_Pos) // prescale PCLK1 = HCLK/2
stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE2_Div1 << stm32.RCC_CFGR_PPRE2_Pos) // prescale PCLK2 = HCLK/1
stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_ADCPRE_Div6 << stm32.RCC_CFGR_ADCPRE_Pos) // prescale ADCCLK = PCLK2/6
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Max ADC clock is 14Mhz, set it to 12MHz

stm32.RCC.CR.SetBits(stm32.RCC_CR_HSEON) // enable HSE clock

// wait for the HSEREADY flag
for !stm32.RCC.CR.HasBits(stm32.RCC_CR_HSERDY) {
Expand Down
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