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spike target fixes for rvv
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PhilippvK committed Nov 25, 2024
1 parent cf7f004 commit 7907623
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Showing 2 changed files with 9 additions and 4 deletions.
9 changes: 7 additions & 2 deletions mlonmcu/target/riscv/riscv.py
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@
#
"""MLonMCU RISC-V Target definitions"""

import re
from pathlib import Path

from mlonmcu.logging import get_logger
Expand Down Expand Up @@ -81,12 +82,16 @@ def reconfigure(self):

@property
def riscv_gcc_prefix(self):
arch = self.arch
arch_ = re.sub(r"_zvl\d+b", "", arch)
ret = Path(
pick_first(
self.config,
[
f"riscv_gcc_{self.arch}_{self.abi}.install_dir",
f"riscv_gcc_{self.arch}.install_dir",
f"riscv_gcc_{arch}_{self.abi}.install_dir",
f"riscv_gcc_{arch_}_{self.abi}.install_dir",
f"riscv_gcc_{arch}.install_dir",
f"riscv_gcc_{arch_}.install_dir",
f"riscv_gcc_rv{self.xlen}.install_dir",
"riscv_gcc.install_dir",
],
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4 changes: 2 additions & 2 deletions mlonmcu/target/riscv/util.py
Original file line number Diff line number Diff line change
Expand Up @@ -223,8 +223,8 @@ def update_extensions(
else:
assert fpu == "double"
require.add("v")
# if vlen:
# require.add(f"zvl{vlen}b")
if vlen:
require.add(f"zvl{vlen}b")

if not minimal:
if fpu in ["single", "double"] and not minimal:
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