Add complexity for sync case

tuura · May 14, 2018 · 0db5445 · 0db5445
1 parent ffca266
commit 0db5445
Showing 1 changed file with 8 additions and 4 deletions.
diff --git a/slides/index.htm b/slides/index.htm
@@ -242,7 +242,8 @@ <h1 style="font-size: 55px; line-height: 125%; margin-top: 200px;">
 
 ## Synchronous Traversal .subslide[(2/3)]
 
-*Breadth-first search on FPGAs*
+*Breadth-first search on FPGAs*: a network with diameter *D* requires *O(D)*
+clock cycles
 
 <center>
 	<img class="fdl-slide" src="figures/fdl_slide_15.svg"/>
@@ -254,7 +255,8 @@ <h1 style="font-size: 55px; line-height: 125%; margin-top: 200px;">
 
 ## Synchronous Traversal .subslide[(2/3)]
 
-*Breadth-first search on FPGAs*
+*Breadth-first search on FPGAs*: a network with diameter *D* requires *O(D)*
+clock cycles
 
 <center>
 	<img class="fdl-slide" src="figures/fdl_slide_16.svg"/>
@@ -266,7 +268,8 @@ <h1 style="font-size: 55px; line-height: 125%; margin-top: 200px;">
 
 ## Synchronous Traversal .subslide[(2/3)]
 
-*Breadth-first search on FPGAs*
+*Breadth-first search on FPGAs*: a network with diameter *D* requires *O(D)*
+clock cycles
 
 <center>
 	<img class="fdl-slide" src="figures/fdl_slide_17.svg"/>
@@ -278,7 +281,8 @@ <h1 style="font-size: 55px; line-height: 125%; margin-top: 200px;">
 
 ## Synchronous Traversal .subslide[(2/3)]
 
-*Breadth-first search on FPGAs*
+*Breadth-first search on FPGAs*: a network with diameter *D* requires *O(D)*
+clock cycles
 
 <center>
 	<img class="fdl-slide" src="figures/fdl_slide_18.svg"/>